HD74 Search Results

Hitachi DSA0095

Abstract: DP-14 FP-14DA FP-14DN HD74HC30 TTP-14D
Contextual Info: HD74HC30 8-input NAND Gate ADE-205-416 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Contextual Info: HD74HCT640 Octal Bus Transceivers with inverted 3-state outputs Octal Bus Transceivers (with 3-state outputs) REJ03D0672–0300 (Previous ADE-205-562A) Rev.3.00 Mar 30, 2006 Description The HD74HCT640 has one active low enable input (G), and a direction control (DIR). When the DIR input is high,

Contextual Info: HD74HCT620, HD74HCT623 Octal Bus Transceivers with inverted 3-state outputs Octal Bus Transceivers (with 3-state outputs) REJ03D0671–0200 (Previous ADE-205-561) Rev.2.00 Mar 30, 2006 Description This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control

Contextual Info: HD74LS390 Dual Decade Counters REJ03D0485-0400 Rev.4.00 May 10, 2006 This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters. The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle

Contextual Info: HD74LS165A Parallel-Load 8-bit Shift Register REJ03D0449–0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /

Hitachi DSA0095

Abstract: 1B10 1B12 HD74ALVCH16269
Contextual Info: HD74ALVCH16269 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs ADE-205-136 Z Preliminary 1st. Edition May 1996 Description The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between

HD74HC00

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D
Contextual Info: HD74HC00 Quad. 2-input NAND Gates ADE-205-403 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 8.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Hitachi DSA00104

Abstract: HD74ALVC162831
Contextual Info: HD74ALVC162831 1-bit 4-bit Address Register / Driver with 3-state Outputs ADE-205-200 Z Preliminary 1st. Edition November 1997 Description This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The

Hitachi DSA0095

Abstract: DP-14 FP-14DA FP-14DN HD74HCU04A TTP-14D
Contextual Info: HD74HCU04A Hex Inverters ADE-205-288 Z 1st. Edition Jun. 1999 Description The HD74HCU04A has six inverters in a 14 pin package. Y = A Features • VCC = 4.5 to 5.5 V operation • Input terminal has protection diode Function Table Input A Output Y H L L

2Y16

Abstract: 1y14 Hitachi DSA00104 HD74ALVC16830 2Y14
Contextual Info: HD74ALVC16830 1-bit to 2-bit Address Driver with 3-state Outputs ADE-205-198 Z Preliminary 1st. Edition November 1997 Description This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V VCC operation. To ensure the high impedance state during power up or power down, the output ebable ( ) input should be tied to VCC

HD74HC05

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D
Contextual Info: HD74HC05 Hex Inverters with Open Drain Outputs ADE-205-407 (Z) 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 8 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

Contextual Info: HITACHI/ L O G I C / A R RA YS /M EM T2 , _ . D E I 4MtihSD3 001D37S 0 | ~ ~ 92D HD74HC123A # Dual Retriggerable Monostable Multivibrators with Clear This multivibrator features both a negative. A, and a positive, • PIN ARRANGEMENT B, transition triggered input, either of which can be used as

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM Ì2 dÊ J 44^303 0D1D44L. A | - HD74HC195 92D 10446 # 4-bit Parallel-Access Shift Register This shift register feetures parallel inputs, parallel outputs, J-K serial inputs, S hift/L oad control input, and a direct | D T- Hb -O l-ß S

Contextual Info: H I T A C H I / LOGIC/ARRAYS/flEH ^5 4 4 ^ 5 0 3 0010b44 1 92D HD 74H C T240 # 10644 D ]~'SZ-<>7 Octal B u ffers/Line D rivers/L ine Receivers with inverted 3-state outputs PIN ARRANGEMENT The HD74HCT240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently con­

Contextual Info: HD74SSTL16857 14-bit SSTL_2 Registered Buffer HITACHI ADE-205-223B Z Preliminary 3rd. Edition February 1999 Description The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM HD74HCT137 TB DE 4 4 ^ 2 0 3 # 3-to-8-line Decoder/Dem ultiplexer with Address Latch | PIN ARRANGEMENT r-J-a T - , T ¡ ] Vcc B[T - B c^ - C Yi u jy. GL Yi ÏÏ]V i G L^ - A Yfl - C¡ Yi ¡ 2] Yi G i^ - Gi

Contextual Info: Ï Ë J 4 4 cit,2D3 G G 1 D 3 S 7 1 J H I T A C H I / L O G I C / A R R A Y S / N E M "il 92D HD74HC91 üT-ïé-ûf-O 10357 • 8 - bit Shift Register This serial-in, serial-out, 8-bit shift register is composed o f eight R-S master-slave flip-flo ps, inpu t gating, and a clock

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / M E M ^2 D Ë J 4 MTticüOB OQlQSfl? 4 D T "H611 92D 10587 HD74HC678 16-bit Address Comparator The H D 7 4 H C 6 7 8 address comparator simplifies addressing of | P IN A R R A N G E M E N T m em ory boards and/or other peripheral devices. The four P

Contextual Info: "HITACHI/ L O G I C / A R RA YS /M En TS D E I 4 4 ^ 5 0 3 DD Id 3 Mb 4 | .9 2 D HD74HC76 • 10346 D T ~ Ÿ é ~ â 7 -û 7 Dual J-K Flip-Flops with Preset and Clear • PIN ARRANGEMENT Each flip -flo p has independent J, K , preset, clear, and clock

Contextual Info: Ì5 HITACHI/ LOGIC/ARRAYS/MEM DE] 4 4 ^ 5 0 3 0GlD3b3 92D HD74HC107 4 |~ V T ~ lf b ~ '0 7 - '0 7 10363 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse.

Contextual Info: HITACHI/ LOGI C / A R R A Y S/ M E M la HD74HC4060 D Ë J *44^203 O O l D b m 92D I VT-V5-2.3-n 10 61 4 # 14-stage Binary Counter The HD74HC4060 is a 14 stage counter, this device increments on the falling edge negative transition of the input | I PIN ARRANGEMENT