GS8182S18 Search Results

Contextual Info: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8182S18D-250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS8182S18

Abstract: GS8182S18D-167 GS8182S18D-200 GS8182S18D-250 GS8182S18D-250I GS8182S18D-267
Contextual Info: GS8182S18D-267/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 267 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8182S18D-250/200/167 SigmaRAM Family Overview me nd ed for Ne w GS8182S18 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit 18Mb SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed

GS8182S36D-167

Abstract: GS8182S36D-200 GS8182S36D-250 GS8182S36D-300 GS8182S36D-333I
Contextual Info: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8182S18/36D-330/300/250/200/167/133 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 133 MHz–330 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8182S18D-250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS8182S36D-200

Abstract: GS8182S36D-250 GS8182S36D-300
Contextual Info: Preliminary GS8182S18/36D-333/300/250/200/167 18Mb Σ2x1B2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS8182S18

Abstract: GS8182S18D-167 GS8182S18D-167I GS8182S18D-200 GS8182S18D-200I
Contextual Info: GS8182S18D-200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 200 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: GS8182S08/09/18/36BD-400/375/333/300/250/200/167 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

K7A803609B-PC25

Abstract: K7A403600B-PC16 K7I161882B-EC16 K6R4016V1D-TC08 K7A403600M-QC16 K7I161882B-EC30 K6R4008V1C-JC12 K6R4016V1D-UC10 K6R1008V1C-JC10 K7R643682M-FC20
Contextual Info: SAMSUNG # - Connect pin 14 FT pin to Vss * - Tie down extra four I/Os with resistor K6R1016V1C-FC10 K6R1016V1C-FC12 K6R1016V1C-FC15 K6R1016V1C-FC20 K6R1016V1C-JC10 K6R1016V1C-JC12 K6R1016V1C-JC15 K6R1016V1C-JC20 K6R1016V1C-TC10 K6R1016V1C-TC12 K6R1016V1C-TC15

GS8182S18BD-167

Abstract: GS8182S18BD-200 GS8182S18BD-250 GS8182S18BD-300
Contextual Info: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

GS8182S18BD

Contextual Info: Preliminary GS8182S08/09/18BD-333/300/250/200/167 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

CY7C1338-100AXC

Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
Contextual Info: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12

UPD44164185F5-E60-EQ1

Abstract: UPD44165362F5-E60-EQ1 UPD444016LG5-A12-7JF UPD4482161GF-A85 UPD44325094F5-E33-EQ2 uPD431232ALGF-A10 uPD431232ALGF-A12 uPD431232ALGF-A7 uPD431232ALGF-A8 uPD431532LGF-A10
Contextual Info: NEC * - Tie down extra four I/Os with resistor uPD4382321GF-A85 GS880F32BT-7.5 + - Tie down extra two I/Os with resistor uPD4382321GF-A90 GS880F32BT-7.5 uPD4382322GF-A67 GS88032BT-200 UPD4311231LGF-A7 GS81032AT-5 uPD4382322GF-A75 GS88032BT-150 UPD4311231LGF-A8

Contextual Info: GS8182S08/09/18/36BD-400/375/333/300/250/200/167 18Mb Burst of 2 SigmaSIO DDR-IITM SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8182S08/09/18/36BD-400/375/333/300/250/200/167 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 18Mb Burst of 2 DDR SigmaSIO-II SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package

GS8673EQ

Abstract: SIGMA SigmaQuad-IIIe GS8673ED36 5502M GS8322Z36 GS816032 GS8171DW GS8673ET36 GS8673ED18
Contextual Info: Untitled3.fm Page 1 Tuesday, March 30, 2010 10:58 AM Untitled4.fm Page 1 Tuesday, March 30, 2010 11:08 AM SigmaQuad_2010_0408.fm Page 3 Thursday, April 15, 2010 11:44 AM SigmaQuad-IIIe SRAMs 72Mb SigmaQuad-IIIe+ Config GS8673ED37Ayy-### GS8673ED19Ayy-### 2M x 36

GS8640Z36

Abstract: GS840Z18A GS816032 GS8342T36 GS8662Q18
Contextual Info: Untitled3.fm Page 1 Wednesday, September 10, 2008 12:03 PM toc.fm Page 1 Wednesday, September 10, 2008 11:05 AM Untitled1.fm Page 1 Wednesday, September 10, 2008 11:32 AM SigmaQuad_new_20080904.fm Page 4 Wednesday, September 10, 2008 11:04 AM SigmaQuad/ CIO/SIO

GS818

Abstract: DDR pinout GS8182S08BD-167 GS8182S08BD-200 GS8182S08BD-250 GS8182S08BD-300
Contextual Info: GS8182S08/09/18/36BD-400/375/333/300/250/200/167 18Mb Burst of 2 SigmaSIO DDR-IITM SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO Interface • JEDEC-standard pinout and package