DS100 Search Results

DS100BR210

Abstract: 10G-KR
Contextual Info: DS100BR210 Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output De-Emphasis General Description Features The DS100BR210 is an extremely low power, high performance dual-channel repeater for serial links with data rates up to 10.3 Gbps. The DS100BR210 is configured as two unidirectional channels.

54AC05

Abstract: AC05 E20A J14A W14B
Contextual Info: 54AC05 Hex Inverter with Open Drain Outputs General Description Features The ’AC05 contains six inverters. n Outputs sink 24 mA n Open drain for wired NOR function n Standard Microcircuit Drawing SMD 5962-9059001 Logic Symbol IEEE/IEC DS100981-1 Connection Diagrams

DS1666

Abstract: DS2011D 74F04 DS1003 DS1003-16 DS1003-20 DS1003-25 DS1003-33 DS1003-40 DS1003M
Contextual Info: DS1003 DS1003 DALLAS SEMICONDUCTOR FEATURES 4-Tap Silicon Delay Line for RISC A pplications PIN ASSIGNMENT • All-silicon tim e delay IN • Four delayed clock phases from input NC • Input frequency independent NC NC • Precise tap-to-tap delays • Leading and trailing edge precision

XC5VLX50T-1FFG665C

Abstract: ff1156 VIRTEX-5 DDR2 controller FFG1156 VIRTEX-5 DDR PHY Virtex-5 Ethernet development Virtex-5 LXT Ethernet DSP48E SRL16 XC5VLX220
Contextual Info: R DS100 v5.0 February 6, 2009 Virtex-5 Family Overview Product Specification General Description The Virtex -5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice

clause 22 phy registers

Abstract: 13007 h3 ali 3602 detail of D 13007 K mca exam date sheet 1000BASE-X DS1005 STS-48
Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1

Contextual Info: DS1007 DS1007 DALLAS SEMICONDUCTOR 7-in-1 Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon time delay • 7 independent buffered delays • Delay tolerance ± 2 ns IN 4 OUT4 • Four delays can be custom set between 3 ns and 10 ns GND OUT7 • Three delays can be custom set between 9 ns and

Contextual Info: D S 1000 DALLAS DS1000 5-Tap Silicon Delay Line SEMICONDUCTOR PIN ASSIGNMENT FEATURES • All-silicon time delay IN [ 1 T 7 14 D Vce IN £ 1 NC NCC 2 • 5 taps equally spaced NC[ 2 13 ] • Delays are stable and precise n c[ 12 ] TAP 1 3 TAP 2 £ 4 • Both leading and trailing edge accuracy

Contextual Info: RELIABILITY MONITOR PRODUCT MONITOR DATE DATE CODE ASSEMBLY FACILITY ASSEMBLY LOT NO PROCESS TYPE PACKAGE TYPE DS1000M-25 May-96 9612 E2 OMEDATA DD547317AGA 1.2µ NITRIDE 08 PDIP STRESS/JOB NO. Infant / High Voltage Life 125°C, 7.0 V. P-17479, P-17575 READPOINT

27014QS

Abstract: 5962R9059001SZA
Contextual Info: 54AC05 Hex Inverter with Open Drain Outputs General Description Features The ’AC05 contains six inverters. n Outputs sink 24 mA n Open drain for wired NOR function n Standard Microcircuit Drawing SMD 5962-9059001 Logic Symbol IEEE/IEC DS100981-1 Connection Diagrams

74ls series

Abstract: 74F04 74LS DS1000 DS1000M DS1000Z
Contextual Info: DS1000–IND DS1000–IND Industrial Temperature Range 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon time delay • 5 taps equally spaced IN 1 14 Vcc NC 2 13 NC • Delays are stable and precise NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3

DS1425L-F5

Abstract: rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S
Contextual Info: ORDERING INFORMATION DEVICE DS0621–SDK DS0630 DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC

Contextual Info: ADVANCE INFORMATION March 7, 2012 Low Power, Dual Lane Thunderbolt Retimer General Description Features The DS100TB211 is a dual lane low power bi-directional retimer with integrated signal conditioning for Thunderbolt cable and peripheral applications. The DS100TB211 includes a fully adaptive input Continuous Time Linear Equalizer CTLE ,

MEC101

Abstract: MEC120 D-MPM101 IPS battery MEC102 MEC101-7P LiCoO2
Contextual Info: THINERGY MEC101 Solid-State, Flexible, Rechargeable Thin-Film Micro-Energy Cell DS1001 v3.4 Product Data Sheet Features • • • • • • • • • Thin Form Factor – 170 µm Thick Capacity options up to 1 mAh All Solid-State Construction High Discharge Rate Capability

pt45

Contextual Info: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks

Contextual Info: RELIABILITY MONITOR PRODUCT MONITOR DATE DATE CODE ASSEMBLY FACILITY ASSEMBLY LOT NO PROCESS TYPE PACKAGE TYPE DS1000M-25 May-97 9710 E3 OMEDATA DD647404AEB 1.2µ NITRIDE 08 PDIP STRESS/JOB NO. Infant / High Voltage Life 125°C, 7.0 V. P-19649, P-19698 READPOINT

19143

Contextual Info: RELIABILITY MONITOR PRODUCT MONITOR DATE DATE CODE ASSEMBLY FACILITY ASSEMBLY LOT NO PROCESS TYPE PACKAGE TYPE DS1000M-25 Feb-97 9649 E3 OMEDATA DD633534ADA 1.2µ NITRIDE 08 PDIP STRESS/JOB NO. Infant / High Voltage Life 125°C, 7.0 V. P-19036, P-19141 READPOINT

DS125RT410

Contextual Info: DS100RT410 www.ti.com SNLS448 – JANUARY 2013 DS100RT410 Low Power 10GbE Quad Channel Retimer Check for Samples: DS100RT410 FEATURES – DS100RT410 EQ+CDR+DE : 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps

Contextual Info: DS100BR410 www.ti.com SNLS326B – OCTOBER 2010 – REVISED APRIL 2013 DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and DeEmphasis Driver Check for Samples: DS100BR410 FEATURES APPLICATIONS • • • • • 1 2 • • • •

Contextual Info: DS100MB201 DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization Literature Number: SNLS333 DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization General Description Features The DS100MB201 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for

Contextual Info: DS100MB201 www.ti.com SNLS333A – APRIL 2011 – REVISED APRIL 2013 DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization Check for Samples: DS100MB201 FEATURES DESCRIPTION • • • The DS100MB201 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning

DS1009J

Abstract: 16J3 TN1137 dsp-219 TN1141 LVCMOS25
Contextual Info: Aug. 2012 LatticeXP2 データシート LatticeXP2 ファミリ・データシート DS1009J Version 01.8b, August 2012 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders.

417 847

Contextual Info: DS1006J_ver3.9 Jan. 2012 あ LatticeECP2/M ファミリ・データシート DS1006J Version 03.9, Jan. 2012 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders.

Contextual Info: DS100MB203 www.ti.com SNLS396A – JANUARY 2012 – REVISED JUNE 2012 DS100MB203 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer with Equalization and DeEmphasis Check for Samples: DS100MB203 FEATURES DESCRIPTION • The DS100MB203 is a dual port 2:1 multiplexer and

DS125RT410

Contextual Info: DS100RT410 www.ti.com SNLS448 – JANUARY 2013 DS100RT410 Low Power 10GbE Quad Channel Retimer Check for Samples: DS100RT410 FEATURES – DS100RT410 EQ+CDR+DE : 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps