DN74LS10 Search Results

DN74LS10

Abstract: MA161
Contextual Info: I LS TTL DN74LS Series DN74LS10 DN74LS10 T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P,j = 6mW typical High speed ( tpd = 10ns typical)

DN74LS109

Abstract: MA161 j-k flip flop clock toggle
Contextual Info: LS TTL DN74LS Series DN74LS109 DN74LS109 J07 Dual J-K P ositive Edge-Triggered F lip-F lops with S et and Reset • Description P -2 D N 7 4 L S 1 0 9 c o n ta in s tw o p o sitive-edge trig g ered J-K flip ­ flo p c irc u its, each w ith in d e p e n d e n t clock-C P, J, K , and

DN74LS10

Abstract: MA161
Contextual Info: LS TTL DN74LS Series DN74LS10 DN74LS10 bio74-LSto T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption Pd = 6mW typical High speed ( tpd = 10ns typical)

Contextual Info: LS TTL DN74LS Series DN74LS107 DN74LS107 ^7^10 7 Dual J-K F lip -F lo p s with Reset • Description P-1 D N 7 4 L S 1 0 7 c o n ta in s tw o negative-edge trig g ered J-K flip ­ flo p c irc u its, each w ith in d e p e n d e n t clock-C P , J , K , and

Contextual Info: LS TTL DN74LS Series DN74LS107 DN74LS107 ^7<RSic>7 Dual J-K F lip -F lo p s with Reset • Description DN74LS107 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled reset input terminals. ■

74LS109

Contextual Info: LS TTL DN74LS Series DN74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered Flip-Flops with Set and Reset P-2 • Description DN 74LS109 contains tw o positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.

Contextual Info: LS TTL DN74LS Series DN74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered F lip-F lops with S et and Reset • Description P-2 D N74LS109 contains two positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.

DN74LS107

Abstract: MA161
Contextual Info: DN74LS107 LS TTL DN74LS Series DN74LS107 ^ 7^10 7 Dual J-K F lip -F lo p s with Reset • Description P-1 D N 7 4 L S 1 0 7 c o n ta in s tw o negative-edge trig g ered J-K flip ­ flo p c irc u its, each w ith in d e p e n d e n t clock-C P , J , K , and

jk flipflop

Abstract: DN74LS107 MA161
Contextual Info: I LS TTL DN74LS Series DN74LS107 D N 74LS107 Dual J-K Flip-Flops with Reset P-1 • Description DN74LS107 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled reset input terminals. ■ Features

Contextual Info: I LS TTL DN74LS Series DN74LS10 DN74LS10 Triple 3 - input P ositive NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P^ = 6mW typical High speed ( tpd = 10ns typical)

Contextual Info: DN74LS10 LS TTL DN74LS Series DN74LS10 t>i0 7<q-lSio T r ip le 3-input P o sitiv e NAND G ates • Description D N 7 4 L S 1 0 co n tain s three 3-in put p ositive iso latio n N A N D gate circuits. ■ Features • L ow p o w e r co n su m p tio n P d = 6mW ty p ic a l

Contextual Info: LS TTL DN74LS Series DN74LS107 D N 7 4 LS 107 Dual J-K Flip-Flops with Reset • Description P-1 DN74LS107 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled reset input terminals. ■ Features

DN74LS109

Abstract: MA161
Contextual Info: LS T T L DN74LS Series DN74LS109 DN74LS109 Dual J-K Positive Edge-Triggered Flip-F lops with S et and Reset • Description P-2 DN74LS109 contains two positive-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals.

Contextual Info: LS T T L DN74LS Series D N 7 4 L S 1 DN74LS109 9 Dual J-K Positive Edge-Triggered Flip-F lops with S et and Reset • Description P-2 DN74LS109 contains two positive-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals.

an6512n

Abstract: mn1225 MN1280 mn6520 MN6130 MN1201A MN6147C MN12C261D MN12C201D MN3107
Contextual Info: <Maintenance Types> This product is not dealt with anymore. Customers dealing with this product conventionally may contact our sales division in the case of ambiguity. <Scrapped Types> Apart from the inquiry concerning repair parts, we will refrain from taking any counteraction.

MN1280

Abstract: AN6512 MN15814 MN15245 2Sb1163a mn158413 AN7210 AN7226 MN15287 MN15283
Contextual Info: pes H Maintenance • mos LS Is Type No. Alternative ^ype No. Alternative Type No. - MN6040Z — - MN6049 — MN3726FE/AE MN4520B/S MN4521 B/S - — MN3726AE MN4522B/S - MN6063 MN6063A - MN4526B/S - MN6064 - - MN4528B/S — - MN4532B/S — MN6064R/S MN61074

MN1873287

Abstract: an6512n 2sk3190 MN171202 mn158413 mn15142 mn187164 mn6740 AN7210 MN15283
Contextual Info: Maintenance and Discontinued Types <Maintenance Types> Maintenance and Discontinued Types This product is not dealt with anymore. Customers dealing with this product conventionally may contact our sales division in the case of ambiguity. <Discontinued Types>