DM74AS11 Search Results

DM74AS11 Datasheets (8)

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Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
DM74AS112J		National Semiconductor	Dual J-K Negative Edge Triggered Flip-Flops with Preset and Clear	Scan	PDF	88.15KB	3
DM74AS112N		National Semiconductor	Dual J-K Negative Edge Triggered Flip-Flops with Preset and Clear	Scan	PDF	88.15KB	3
DM74AS113J		National Semiconductor	Dual J-K Negative Edge Triggered Flip-Flops with Preset	Scan	PDF	81.58KB	3
DM74AS113N		National Semiconductor	Dual J-K Negative Edge Triggered Flip-Flops with Preset	Scan	PDF	81.58KB	3
DM74AS114J		National Semiconductor	Dual J-K Negative Edge Triggered Flip-Flops with Preset, Common Clear and Common Clock	Scan	PDF	88.09KB	3
DM74AS114N		National Semiconductor	Dual J-K Negative Edge Triggered Flip-Flops with Preset, Common Clear and Common Clock	Scan	PDF	88.09KB	3
DM74AS11M		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.	Historical	PDF	42.12KB	1
DM74AS11N		Unknown	Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.	Historical	PDF	42.12KB	1

DM74AS11 Price and Stock

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National Semiconductor Corporation


National Semiconductor Corporation DM74AS11N IC,LOGIC GATE,3 3-INPUT AND,AS-TTL,DIP,14PIN,PLASTIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components ()	DM74AS11N		69			1 - 10 - 100 - 1000 - 10000 -	Buy Now
	DM74AS11N		60			1 $3.38 10 $3.38 100 $1.86 1000 $1.86 10000 $1.86	Buy Now

DM74AS11 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
74AS113 Abstract: S113 Contextual Info: PRELIMINARY Semiconductor DM54AS113/DM74AS113 Dual J-K Negative-EdgeTriggered Flip-Flops with Preset General Description Features The DM54AS113 is a dual-edge-triggered flip -flo p s . Each flip -flo p has individual J, K, clock, and preset inputs, and also com plem entary Q and Q ou tputs.	OCR Scan	dm54as113/dm74as113 dm54as113 dm74as113 tl/f/6286-2 +274as113 s113	PDF
74AS114 Abstract: S114 Contextual Info: DM54AS114/ DM74AS114 5 * \| National £ZA Semiconductor PRELIMINARY DM54AS114/DM74AS114 Dual J-K Negative-EdgeTriggered Flip-Flops with Preset, Common Clear and Common Clock General Description Features The D M 54A S 114 is a d u a l e d g e -trig g e re d flip - flo p . E ach	OCR Scan	dm54as114/dm74as114 dm54as114 dm74as114 tl/f/6287-2 +274as114 s114	PDF
DM74AS11N Contextual Info: NATIONAL SEflICOND -CL06IC3- 31E D • bSD1122 QGt>cîM3G 5 ■ r?n National t^/3 ~t$-oo ÆjA Semiconductor DM74AS11 Triple 3-Input AND Gate ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin for pin compatible with Schottky,	OCR Scan	-cl06ic3-bsd1122 dm74as11 dm74as11n	PDF
national semiconductor TTL Contextual Info: éOà CT1 National Semiconductor DM74AS11 Triple 3-Input AND Gate Advanced oxide-isolated, ion-implanted Schottky TTL process Functionally and pin for pin compatible with Schottky, low power Schottky, and advanced low power Schottky TTL counterpart Improved AC performance over Schottky, low power	OCR Scan	dm74as11 dm74as1 national semiconductor ttl	PDF
74AS112 Abstract: DM54AS1121DM74AS112 S112 Contextual Info: DM54AS 112/ DM74AS 112 PRELIMINARY %9A National ÆjA Semiconductor DM74AS112 Dual J-K Negative-EdgeTriggered Flip-Flops with Preset and Clear General Description Features The 0M 54AS112 is a dual edge-triggered flip -flo p . Each flip -flo p has individual J, K, c lo c l^ c le a r and preset inputs,	OCR Scan	dm54as1121dm74as112 0m54as112 dm54as112 dm74as112 +3tl/f/6285-2 74as112 s112	PDF