DAL01 Search Results

dale r01f

Abstract: MK68H MK68590 r01f dale MK68200 Z8000 MOSTEK ROM r01f mostek MK5025 IN914
Contextual Info: MK5025 P R E L IM IN A R Y C O M M U N IC A T IO N S PR O O U C TS FEATURES DAL04 £ £ 3 £ 4 £ S £ Z Data rate up to 7 MBPS with 64 bytes FIFOs in each direction. DAL03 6 C DA102 7 DAL01 1 H Z Complete Date Link Layer Implementation. DALDQ £ £ 11 £

MK68590

Abstract: Mostek MK5027 DAL00 DAL08 68200 MK5025 mostek clock X25 CCITT DAL12
Contextual Info: é M ♦ k THOMSON COMPONENTS MOSTEK A D IR N C IË COMMUNICATION PRODUCTS D N FO R G M ÎiM G O ft! DATA SHEET MK5027 FEATURES VSS-GND DAL07 DAL06 DAL05 DAL04 DALD3 DALO2 DAL01 DAL00 □ CMOS □ Fully com patible with both 8 or 16 bit systems. C System clock rate to 10 M H z.

80386SX

Abstract: DIP48 MK5025 MK5027 MK50H25 Z8000 dali Receiver 80286 instruction
Contextual Info: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst

Contextual Info: SGS-TtiOMSON MK50H28 • U K ê T IM M Ê i MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES ■ Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs .

mk5021

Abstract: N393 BCNT DIP48 MK5027 MK50H28 PLCC52 Z8000 A 1905 LMI
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

Contextual Info: A m 79C 900 In t e g r a te d L o c a l A re a C o m m u n ic a tio n s C ontroller ILACC™ Distinctive Characteristics. 1-51 General Description. 1-51

N393

Abstract: DIP48 MK50H25 MK50H27 MK50H28 PLCC52 Z8000 DAL13
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

JT-Q703

Abstract: MK50H27Q-33 bsnt1
Contextual Info: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements

Q703

Abstract: DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703 68000 thomson
Contextual Info: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements

mk5021

Abstract: TSW 8088 SRS 4451 DE-A1D
Contextual Info: ^ 7 ^ 7 # « S G S -T H O M S O N IM » iL [Ì g » S l(g § TECHNICAL MANUAL MK5021 SERIAL COMMUNICATIONS CONTROLLER TABLE OF CONTENTS SECTION PAGE SECTION 1 INTRODUCTION Introduction 3 SECTION 2 FEATURES Features 3 SECTION 3 OPERATIONAL DESCRIPTION 3.1 Functional B lo c k s .

MK5025

Abstract: MK5025Q MK50H25 MK50H25Q MK50H25Q16 MK50H27
Contextual Info: APPLICATION NOTE Upgrading From MK5025 to MK50H25 by Darin Kincaid The MK50H25 is a pin for pin replacement for the MK5025 with additional features and performance enhancements. Options such as on-chip watch dog timers and pass through of bad CRCs are available

STR d 4412 PINS DETAILS

Abstract: dali n39l
Contextual Info: SGS-THOMSON iH lM M O e s M K 5 0 H 2 8 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES • Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and Additional Pocedures tor Permanent Virtual Circuits PVCs . ■ Optional Transparent Mode (no LMI Protocol

DIP48

Abstract: MK5021 MK5027 MK50H28 PLCC52 Z8000
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol

DIP48

Abstract: MK50H25 MK50H27 MK50H28 PLCC52 Z8000 BCNT
Contextual Info: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol

mk7990

Abstract: MK5021Q10 marking r01f mk5027q10 CSR 41b datasheet SMD R01f 48-PIN MK5025 PLCC52 mk5021
Contextual Info: • 7^21237 D OMSa ^a 3ñT M S G T H SGS-THOMSON _ MK5025 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A . CMOS ■ FULLY COMPATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE

80486 microprocessor pin out diagram

Abstract: architecture of 80486 microprocessor DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703
Contextual Info: S G S -T H O M S O N ^ D g W [llL i ¥ ^ (Q K 5 0 © S M K 5 0 H 2 7 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols.

MK5021Q10

Abstract: MK5025 MK5025Q MK50H25 MK50H25Q MK50H25Q16 MK50H27 mk5021 mk5021q-10
Contextual Info: APPLICATION NOTE Upgrading From MK5025 to MK50H25 by Darin Kincaid The MK50H25 is a pin for pin replacement for the MK5025 with additional features and performance enhancements. Options such as on-chip watch dog timers and pass through of bad CRCs are available

SRS 4451

Contextual Info: / = T S G S -T H O M S O N MK50H25 HIGHSPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25- 16). ■ Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted

JT-Q703

Abstract: 68000 thomson
Contextual Info: iZ T SGS-THOMSON MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES • Complete Level 2 Implementation ot SS7. ■ Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. ■ Optional operation to comply with Japanese

Contextual Info: H ZT ^7 M S G S -T H O M S O N M fg M ir a F M R Ä S M K50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES • Complete Level 2 Implementation of SS7. ■ Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols.

IN5048

Abstract: Q703 DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703
Contextual Info: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements

MK7990

Abstract: TSW 8088 mk5021q10
Contextual Info: SGS-THOMSON ^ D Û ^ O llL C l'Ê r ^ Q iD 'Ê l M K 5 0 2 5 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A • CMOS . FULLY COM PATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE

Contextual Info: APPLICATION NOTE MK5025 SYNCHRONOUS TIMING INTRODUCTION The SGS-Thomson MK5025 X.25 Link Level Controller is a VLSI device which provides a complete link level data communication control conforming to the 1984 CCITT version of X.25. The MK5025 also supports X.32 XID and X.75 as

MK5025

Abstract: MK5025Q MK50H25 MK50H25Q MK50H25Q16 MK50H27
Contextual Info: APPLICATION NOTE Upgrading From MK5025 to MK50H25 by Darin Kincaid The MK50H25 is a pin for pin replacement for the MK5025 with additional features and performance enhancements. Options such as on-chip watch dog timers and pass through of bad CRCs are available