CY2DP1502 Search Results
CY2DP1502 Datasheets (8)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY2DP1502SXC | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8SOIC | Original | 17 | |||
| CY2DP1502SXCT | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8SOIC | Original | 17 | |||
| CY2DP1502SXI | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8SOIC | Original | 17 | |||
| CY2DP1502SXIT | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8SOIC | Original | 17 | |||
| CY2DP1502ZXC | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8TSSOP | Original | 17 | |||
| CY2DP1502ZXCT | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8TSSOP | Original | 17 | |||
| CY2DP1502ZXI | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8TSSOP | Original | 17 | |||
| CY2DP1502ZXIT | Cypress Semiconductor | Clock/Timing - Clock Buffers, Drivers, Integrated Circuits (ICs), IC CLK BUFFER 1:2 1.5GHZ 8TSSOP | Original | 17 |
CY2DP1502 Price and Stock
Infineon Technologies AG CY2DP1502SXIClock Fanout Buffer 2-OUT 1-IN 1:2 8-Pin SOIC Tube |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY2DP1502SXI | 3,000 | 1,500 |
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Buy Now | ||||||
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CY2DP1502SXI | Tube | 217 |
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CY2DP1502SXI | 3,303 |
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Cypress Semiconductor CY2DP1502ZXCCY2DP1502ZXC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY2DP1502ZXC | 1,024 | 66 |
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CY2DP1502ZXC | 1,024 | 1 |
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Cypress Semiconductor CY2DP1502ZXICY2DP1502ZXI |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY2DP1502ZXI | 825 | 28 |
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| CY2DP1502ZXI | 116 | 28 |
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CY2DP1502ZXI | 941 | 1 |
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Cypress Semiconductor CY2DP1502SXCCY2DP1502SXC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|
CY2DP1502SXC | 770 | 66 |
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| CY2DP1502SXC | 366 | 66 |
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CY2DP1502SXC | 1,136 | 1 |
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CY2DP1502SXC | 3,303 |
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Cypress Semiconductor CY2DP1502SXICY2DP1502SXI |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY2DP1502SXI | 439 | 41 |
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| CY2DP1502SXI | 301 | 41 |
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CY2DP1502SXI | 271 |
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Get Quote | |||||||
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CY2DP1502SXI | 740 | 1 |
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CY2DP1502 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
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Contextual Info: CY2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz |
Original |
cy2dp150220-ps480-ps15-ps+2 | |
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Contextual Info: CY2DP1502 1:2 LVPECL Fanout Buffer Functional Description Features • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz |
Original |
cy2dp150220-ps480-ps15-ps+2 | |
JESD78B
Abstract: cy2d
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Original |
cy2dp150220-ps480-ps15-ps+4 | |
"differential input" common mode voltage LVDS
Abstract: JESD78B
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Original |
cy2dp150220-ps480-ps15-ps+2 | |
JESD78BContextual Info: CY2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz |
Original |
cy2dp150220-ps480-ps15-ps+3 | |
JESD78BContextual Info: CY2DP1502 1:2 LVPECL Fanout Buffer 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input |
Original |
cy2dp150220-ps480-ps15-ps+1 |