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    CD74HC10 Search Results

    CD74HC10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CD74HC107E
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 Visit Texas Instruments Buy
    CD74HC107M96
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HC109M
    Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HC107EE4
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 Visit Texas Instruments Buy
    CD74HC109E
    Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 Visit Texas Instruments Buy

    CD74HC10 Datasheets (115)

    Select Manufacturer
    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CD74HC10
    Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gate Original PDF 39.98KB 6
    CD74HC10
    Texas Instruments High Speed CMOS LogicTriple 3-Input NAND Gate Original PDF 32.55KB 6
    CD74HC107
    Texas Instruments Dual J-K Flip-Flop with Reset Negative-Edge Trigger Original PDF 55.87KB 8
    CD74HC107
    Texas Instruments Dual J-K Flip-Flop with ResetNegative-Edge Trigger Original PDF 45.14KB 8
    CD74HC107E
    Texas Instruments Dual J-K Flip-Flop with Reset Negative-Edge Trigger Original PDF 149.22KB 11
    CD74HC107E
    Texas Instruments Dual J-K Flip-Flop with Reset Negative-Edge Trigger Original PDF 55.87KB 8
    CD74HC107E
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 Original PDF 454.56KB 15
    CD74HC107E
    Texas Instruments CD74HC107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 Original PDF 630.46KB 16
    CD74HC107E
    Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF 32.93KB 1
    CD74HC107E96
    Texas Instruments Dual J-K Flip-Flop with Reset Negative-Edge Trigger Original PDF 45.14KB 8
    CD74HC107EE4
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset Original PDF 290.99KB 13
    CD74HC107EE4
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 Original PDF 454.56KB 15
    CD74HC107EE4
    Texas Instruments CD74HC107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125 Original PDF 630.46KB 16
    CD74HC107EG4
    Texas Instruments Integrated Circuits (ICs) - Logic - Flip Flops - IC FF JK TYPE DUAL 1BIT 14DIP Original PDF 632.95KB
    CD74HC107M
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 Original PDF 454.56KB 15
    CD74HC107M
    Texas Instruments Dual J-K Flip-Flop with Reset Negative-Edge Trigger Original PDF 55.87KB 8
    CD74HC107M
    Texas Instruments CD74HC107 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 Original PDF 630.46KB 16
    CD74HC107M
    Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF 32.93KB 1
    CD74HC107M96
    Texas Instruments Dual J-K Flip-Flop with Reset Negative-Edge Trigger Original PDF 149.22KB 11
    CD74HC107M96
    Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125 Original PDF 454.56KB 15
    SF Impression Pixel

    CD74HC10 Price and Stock

    Texas Instruments

    Texas Instruments CD74HC10E

    NAND Gate 3-Element 3-IN 14-Pin PDIP Tube
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    Verical () CD74HC10E 24,449 759
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    CD74HC10E 4,925 759
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    CD74HC10E 4,160 759
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    CD74HC10E 4,000 759
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    CD74HC10E 3,969 759
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    Mouser Electronics CD74HC10E 382
    • 1 $0.93
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    Rochester Electronics CD74HC10E 41,528 1
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    Texas Instruments CD74HC10M

    NAND Gate 3-Element 3-IN CMOS 14-Pin SOIC Tube
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    Verical () CD74HC10M 13,287 408
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    CD74HC10M 4,406 408
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    CD74HC10M 2,172 408
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    Rochester Electronics CD74HC10M 21,445 1
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    Component Electronics, Inc CD74HC10M 5
    • 1 $1.15
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    Win Source Electronics CD74HC10M 50,000
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    Texas Instruments CD74HC107E

    Flip Flop JK-Type Neg-Edge Push-Pull 2-Element 14-Pin PDIP Tube
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    Verical () CD74HC107E 4,825 458
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    CD74HC107E 4,000 458
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    CD74HC107E 2,925 458
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    CD74HC107E 1,950 458
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    CD74HC107E 1,944 458
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    CD74HC107E 1,000 458
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    CD74HC107E 557 4
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    Mouser Electronics CD74HC107E 1,029
    • 1 $1.33
    • 10 $0.97
    • 100 $0.78
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    • 10000 $0.64
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    Arrow Electronics () CD74HC107E 1,000 12 Weeks 25
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    CD74HC107E 557 1
    • 1 $1.00
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    Quest Components () CD74HC107E 1,071
    • 1 $0.65
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    CD74HC107E 80
    • 1 $0.77
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    Rochester Electronics CD74HC107E 24,538 1
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    TME CD74HC107E 174 1
    • 1 $1.46
    • 10 $1.04
    • 100 $0.84
    • 1000 $0.72
    • 10000 $0.68
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    Texas Instruments CD74HC107M96

    Flip Flops Hi-Spd CMOS Dual Neg J-K Flip-Flop A 595 A 595-CD74HC107M
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics CD74HC107M96 4,560
    • 1 $0.68
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    Arrow Electronics CD74HC107M96 Cut Strips 1,773 1
    • 1 $0.55
    • 10 $0.42
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    Bristol Electronics CD74HC107M96 495 1
    • 1 $0.42
    • 10 $0.42
    • 100 $0.16
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    Quest Components () CD74HC107M96 396
    • 1 $0.96
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    CD74HC107M96 396
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    Rochester Electronics CD74HC107M96 2,500 1
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    TME CD74HC107M96 2,500
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    ComSIT USA CD74HC107M96 4,252
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    Texas Instruments CD74HC10M96

    Logic Gates Triple 3-Input A 595 -CD74HC10M A 595-CD A 595-CD74HC10M
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    Mouser Electronics CD74HC10M96 2,666
    • 1 $0.40
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    Bristol Electronics CD74HC10M96 1,784 1
    • 1 $0.50
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    Win Source Electronics CD74HC10M96 310
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    CD74HC10 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    HC10

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128chc10cd54hc10f3acd54hct10f3acd74hc10e PDF

    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140C Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2003


    Original
    cd54hc109cd74hc109cd54hct109cd74hct109+5schs140chc109hct109cd74hct109 PDF

    Contextual Info: CD74HC107, CD74HCT107 ^ Texas In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immu­ nity and Increased Input Rise and Fall Times


    OCR Scan
    cd74hc107cd74hct107hc/hct73 PDF

    HC107

    Abstract: 74HCT 74LS CD74HC107 CD74HC107E CD74HCT107 CD74HCT107E HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times


    Original
    hc107hct10cd74hc107cd74hct107+5schs13974hct74lscd74hc107ecd74hct107e PDF

    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    cd54hc10cd74hc10cd54hct10cd74hct10+2schs128chct10 PDF

    HCT10

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128ccd54hc10f3acd54hct10f3acd74hc10ehc10 PDF

    CD54HC107

    Abstract: CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HC107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original
    hc107hct10cd54hc107cd74hc107+5cd74hct107schs139dcd54hc107f3acd74hc107ecd74hc107m PDF

    CD54HC10

    Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128ccd54hc10f3acd54hct10f3acd74hc10ehc10 PDF

    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original
    cd54hc107cd74hc107cd74hct107schs139d+2hc107hc/hct73 PDF

    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd54hc109cd74hc109cd54hct109cd74hct109+5schs140ehc109hct109cd74hct109 PDF

    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd74hct109cd54hc109cd74hc109+5cd54hct109cd74hct109schs140ehc109hct109 PDF

    "J-K Flip flop"

    Abstract: CD54HC107F3A HC107 T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original
    hc107hct10cd54hc107cd74hc107+7cd74hct107schs139dj-k flip flopcd54hc107f3at flip flop iccd74hc107ecd74hc107m PDF

    HC107

    Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
    Contextual Info: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, CD74HCT107 Data sheet acquired from Harris Semiconductor SCHS139C Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2003


    Original
    hc107hct10cd54hc107cd74hc107+5cd74hct107schs139ccd54hc107f3acd74hc107ecd74hc107m PDF

    CD54HC10

    Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128bcd54hc10f3acd54hct10f3acd74hc10ehc10 PDF

    C109

    Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109
    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd74hct109cd54hc109cd74hc109+7cd54hct109cd74hct109schs140ehc109hct109c109cd54hc109f3a PDF

    C109

    Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109
    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd74hct109cd54hc109cd74hc109+7cd54hct109cd74hct109schs140ehc109hct109c109cd54hc109f3a PDF

    C109

    Abstract: CD54HC109 CD54HC109F3A CD54HCT109 CD74HC109 CD74HCT109 HC109
    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140D Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised July 2003


    Original
    cd74hct109cd54hc109cd74hc109+7cd54hct109cd74hct109schs140dhc109hct109c109cd54hc109f3a PDF

    D74HC10

    Contextual Info: CD74HC10,0 h a r r is S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-lnput NAND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC10, CD74HCT10, logic gates utilize silicon gate CMOS technology to achieve operating speeds


    OCR Scan
    cd74hc10cd74hct1074hct1-800-4-harris+1d74hc10 PDF

    CD74HC10E

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 HCT10
    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    hct10cd54hc10cd74hc10cd54hct10+6cd74hct10schs128ccd74hc10ecd54hc10f3acd54hct10f3ahc10 PDF

    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd74hct109cd54hc109cd74hc109+5cd54hct109cd74hct109schs140ehc109hct109 PDF

    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd54hc109cd74hc109cd54hct109cd74hct109+5schs140ehc109hct109cd74hct109 PDF

    Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003


    Original
    cd54hc109cd74hc109cd54hct109cd74hct109+5schs140ehc109hct109cd74hct109 PDF

    Contextual Info: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, CD54HCT10, CD74HCT10


    Original
    hct10cd54hc10cd74hc10cd54hct10+2cd74hct10schs128c PDF

    74LS family

    Abstract: HCT73
    Contextual Info: ASSESS? CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immu­ nity and Increased Input Rise and Fall Times The Harris CD74HC107 and CD74HCT107 utilize silicon


    OCR Scan
    cd74hc107cd74hct107hc/hct7374hct+274ls familyhct73 PDF