0588
Abstract: transistor p16 ATL35
Contextual Info: CLA7X ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 7-input carry lookahead Truth Table: ATL55Cells A A B C D E F G | O -X X X X X X 1 | 0 X X X X 1 1 X | 0 X X 1 1 X 1 X | 0 1 1 X 1 X 1 X | 0 X X X X X 0 0 | 1 X X X 0 0 X 0 | 1
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N136
Abstract: n133 MUX8n ATL35 N132 P103 P133 023632 P107N N144
Contextual Info: MUX2 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2:1 MUX Truth Table: S | O -0 | I0 1 | I1 ATL55Cells S MUX2 I0 O I1 VDD! p P14 S n N3 VSS! VDD! p P20 p P23 I0 VDD! n N6 N22 n p P32 VSS! O n VDD! N34 p P16 p P21 I1 n N25 VSS! VDD! N29
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TI P272
Abstract: n326 082269 N294 N324 N322 n373 N327 N364 N343
Contextual Info: DFF ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: D flip-flop Truth Table: CLK D | Q T+1 -RE 0 | 0 RE 1 | 1 FE X | Q(T) ATL55Cells CLK DFF D Q VDD! VDD! n N73 p n N71 P18 N26 p P34 n VSS! VDD! n N25 p p p n P33 N54 P5 p P13
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n111 datasheet
Abstract: n262 p109 N-69 N110 N173 P267 ATL35 N174 P123
Contextual Info: DLY1 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Delay buffer 1.0ns Truth Table: I | O -0 | 0 1 | 1 ATL55Cells I DLY1 O VDD! VDD! p P5 p p P30 VDD! p P19 p p P0 VDD! p P6 P18 p P7 p P17 P25<0:1> I O n n N1 n N8 n N16 N24 n N9 VSS! n N15
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ATL35
Abstract: N109 009318 op4E P55n P25AN CP-19
Contextual Info: NOR2 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2-input NOR Truth Table: A B | O -0 0 | 1 1 X | 0 X 1 | 0 ATL55Cells A NOR2 O B VDD! p A P2 p B P0 O n n N10 VSS! / $Revision: 1.35 $
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P7 transistor
Abstract: ATL35 PP10
Contextual Info: HLD1 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Bus hold cell Truth Table: X | X -0 | weak0 1 | weak1 ATL55Cells HLD1 X VDD! p P0 p P10 p P8 VSS! p P33 p P7 p P34 X n N6 n N24 n N25 VDD! n N12 n N26 n N15 VSS! VDD! p P31 n N19 VSS! / $Revision: 1.35 $
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OAI222
Abstract: OAI22 ATL35 OAI22224 OAI222H 014748 023414 p6 n60 ATL35/208
Contextual Info: OAI22 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2-input OR into 2-input NAND Truth Table: A A B C | O -X X 0 | 1 1 X 1 | 0 X 1 1 | 0 0 0 1 | 1 ATL55Cells B O OAI22 C VDD! p B P11 p A P7 VDD! p P3 O N10 n n n N30 VSS! N29 VSS! C
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AOI222
Abstract: AOI2223 ATL35 AOI2223H AOI222H n38n AOI23
Contextual Info: AND2 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2-input AND Truth Table: A B | O -0 0 | 0 0 1 | 0 1 0 | 0 1 1 | 1 ATL55Cells B AND2 O A VDD! p VDD! p P2 VDD! p P0 P1 O n B n N3 N5 n A N4 VSS! VSS! / $Revision: 1.35 $
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100 n37
Abstract: n37 or gate ATL35 CMOS GATE ARRAY
Contextual Info: BUF2T ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2x tristate bus driver with active high enable Truth Table: E I | O -0 X | Z 1 0 | 0 1 1 | 1 ATL55Cells BUF2T O I E VDD! p P11 VDD! p P4 n N3 p P12 VSS! I O n N5 VDD! N13 VSS! n p VDD! P0
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ATL35
Abstract: P102 truth table nand gate
Contextual Info: NAN2 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2-input NAND Truth Table: A B | O -0 X | 1 X 0 | 1 1 1 | 0 ATL55Cells B NAN2 O A VDD! p VDD! p P4 P13 O n B N3 n A N10 VSS! / $Revision: 1.35 $
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core i3
Abstract: INV8 INV10 core i3 free download CMOS GATE ARRAY ATL35 N38P
Contextual Info: INV1 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 1x inverter Truth Table: I | O -0 | 1 1 | 0 INV1 ATL55Cells1X I O VDD! p P5 I O n N4 VSS! / $Revision: 1.35 $ Mon Oct 20 15:33:06 1997
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ATL35
Abstract: BUF3 p60n ATL35/208
Contextual Info: BUF1 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 1x buffer Truth Table: ATL55Cells 1X I I | O -0 | 0 1 | 1 BUF1 O VDD! p VDD! p P0 P2 I O n n N3 N4 VSS! VSS! / $Revision: 1.35 $
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P30 CORE N48
Abstract: n38n ATL35 latr CMOS GATE ARRAY
Contextual Info: LAT ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: LATCH Truth Table: H D | Q T+1 -0 0 | 0 1 | 1 1 X | Q(T) ATL55Cells H LAT D Q VDD! VDD! p P58 p P53 p P62 D Q n n N59 N52 N63 n VSS! VSS! VDD! N56 n p P57 p P65 VDD! n VDD!
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002748
Abstract: n191 N246 P259 n227 n232 P247 N101 N109 P103
Contextual Info: DEC4 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: 2:4 decoder Truth Table: S1 S0 | D3 D2 D1 D0 -0 0 | 1 1 1 0 0 1 | 1 1 0 1 1 0 | 1 0 1 1 1 1 | 0 1 1 1 ATL55Cells DEC4 S0 D0 S1 D2 D1 D3 VDD! VDD! p p VDD! P95 p P97 D0 P92
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