AND8009 Search Results

k1117

Abstract: R36W power transistor k1821 L46R k1518 k1117 transistor k2225 transistor k2225 k1317 transistor k1317
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS

R36W

Abstract: k1420 N52C N38C l46r k0114 N53C transistor k1117 k2225 transistor transistors k2628
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information

transistor r1010

Abstract: 555N pw-3n BF 245 A spice BF172 MJE 280 power transistor TT2120 BF192 transistor r1011 transistor D113
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective Schematic Information The objective of ”AND8009 ECLinPS Plus SPICE Modeling Kit” is to provide sufficient circuit schematic and

k1213

Abstract: k1118 transistor k1317 k1117 K2225 k2225 transistor k0305 K0319 c1213 transistor k1117 transistor
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information

k2324

Abstract: k1821 k2225 k1317 power transistor k1821 k1213 k1117 k0313 k2225 transistor N13R
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS

k1213

Abstract: K1118 k0312 k2225 transistor transistors k0317 transistors k2628 K1020 c1213 transistor transistor k1213 K1117
Contextual Info: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman, Paul Hunt ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The Objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information

LQFP32

Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs

MC100EP90

Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Contextual Info: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

N100

Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

KEP05

Abstract: HEP05 MC100EP05 MC10EP05
Contextual Info: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance

LVEP221

Abstract: NB100LVEP221 NB100LVEP221FA NB100LVEP221FAR2
Contextual Info: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential

HEP58

Abstract: MC100EP58 MC10EP58
Contextual Info: MC10EP58, MC100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical

MC100

Abstract: MC100E016 MC100EP016 MC100EP016A MC100EP016AFA MC100EP016AFAR2 25pe16
Contextual Info: MC100EP016A 3.3 VĄECL 8-Bit Synchronous Binary Up Counter The MC100EP016A is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the ECLinPS family MC100E016 with higher operating speed.

EP809

Abstract: MC100EP809 MC100EP809FA MC100EP809FAR2 MC100 SY89809L
Contextual Info: MC100EP809 3.3VĄ1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable The MC100EP809 is a low skew 1–to–9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage

D1875

Abstract: HVP16 KVP16 LVEL16 MC100LVEP16 MC10LVEP16
Contextual Info: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16

AND8020

Abstract: AND8040 MC100EP40 MC100EP40DT MC100EP40DTR2 j 3055
Contextual Info: MC100EP40 3.3V / 5VĄECL Differential Phase-Frequency Detector The MC100EP40 is a three–state phase–frequency detector intended for phase–locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design

EP105

Abstract: MC100EP105 MC100EP105FA MC100EP105FAR2 MC10EP105 MC10EP105FA MC10EP105FAR2 marking CODE D2B
Contextual Info: MC10EP105, MC100EP105 3.3V / 5VĄECL Quad 2-Input Differential AND/NAND The MC10/100EP105 is a quad 2–input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device,

MC10EP01

Contextual Info: MC10EP016, MC100EP016 3.3V / 5VĄECL 8-Bit Synchronous Binary Up Counter The MC10/100EP016 is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD

Contextual Info: MC10EP451, MC100EP451 Product Preview 3.3V / 5VĄECL 6-Bit Differential Register with Master Reset The EP451 is a 6–bit fully differential register with common clock and single ended Master Reset MR . It is ideal for very high frequency applications where a registered data path is necessary.

LQFP-64

Abstract: LVEP224 NB100LVEP224 NB100LVEP224FA NB100LVEP224FAR2
Contextual Info: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low

EP11

Abstract: HEP11 KEP11 LVEL11 MC100EP11 MC10EP11
Contextual Info: MC10EP11, MC100EP11 3.3V / 5V ECL 1:2 Differential Fanout Buffer The MC10/100EP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the LVEL11 device. With AC performance much faster than the LVEL11 device, the EP11 is ideal

Contextual Info: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the

PS2360

Contextual Info: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further

Contextual Info: MC10EP17, MC100EP17 3.3V / 5VĄECL Quad Differential Driver/Receiver The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high