8193RD Search Results

Contextual Info: SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695A – JUNE 2003 – REVISED JUNE 2003 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication

SN74V273

Abstract: SN74V273-EP SN74V273PZAEP SN74V283 SN74V283-EP SN74V293 SN74V293-EP SN74V263 SN74V263-EP SN74V263PZAEP
Contextual Info: SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695 – JUNE 2003 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication

C2658

Abstract: C2653 C265 CY7C265 la 4127
Contextual Info: CY7C265 » r CYPRESS 8K X 8 Registered PROM Features Functional Description • • T h e C Y 7C 265 is a 8192 x 8 re g iste re d P R O M . It is o rg a n iz e d as 8,192 w o rd s by 8 b its w ide, a n d h a s a p ip e lin e o u tp u t re g ­ iste r. In a d d itio n , th e d evice fe a tu re s a

Contextual Info: SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695A – JUNE 2003 – REVISED JUNE 2003 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication

Contextual Info: SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695A – JUNE 2003 – REVISED JUNE 2003 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication

Contextual Info: SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695A – JUNE 2003 – REVISED JUNE 2003 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication

SN74V263

Abstract: SN74V263-6 SN74V273 SN74V273-6 SN74V283 SN74V283-6 SN74V293
Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669A – JUNE 2001 – REVISED AUGUST 2001 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

SN74V263

Abstract: SN74V263-6 SN74V273 SN74V273-6 SN74V283 SN74V283-6 SN74V293
Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

SN74V263

Abstract: SN74V263-6 SN74V273 SN74V273-6 SN74V283 SN74V283-6 SN74V293
Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

Contextual Info: CY7C268 CY7C269 p y p p p rc c 64K Registered Diagnostic PROM SEMICONDUCTOR Features Functional Description • C M O S for optimum speed/ power T he CY7C268 an d C Y 7C 269 are 64K R egistered D iagnostic P R O M s. T hey are both organized 8192 w ords by 8

SPRA547

Abstract: v273 SN74V263 SN74V263-EP SN74V263PZAEP SN74V273 SN74V273-EP SN74V273PZAEP SN74V283 SN74V283-EP
Contextual Info: SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS695A – JUNE 2003 – REVISED JUNE 2003 D D D D D D D D D D D D D D D Controlled Baseline – One Assembly/Test Site, One Fabrication

Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

C2653

Abstract: C2659 C2652 CY7C265 SAAB
Contextual Info: CYPRESS SEMICO NDUCTOR 4bE D B 250^2 Q D 0 b 7 ci3 5 E3C YP ^ V - ^ - v b - z r ] mSÈÊÆ CYPRESS s? SEMICONDUCTOR CY7C265 8192 x 8 Registered PROM Features Functional Description • CMOS for optimum speed/power • Highspeed — 15psm ax. set-up — 12 ns clock to output

Contextual Info: CY7C265 CYPRESS SEMICONDUCTOR Features • CMOS for optimum speed/power • High speed commercial and military — 15 ns max. set-up — 1 2 ns clock to output • Low power — 660 mW (commercial) — 770 mW (military) • On-chip edge-triggered registers

Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

Contextual Info: CY7C265 pypptTQC 64K Registered PROM SEMICONDUCTOR Features • Slim , 300 m il 28 pin plastic or herm etic D IP • CMOS for optimum speed/ power • High speed — 40 ns max set-up — 20 ns clock to output Functional Description T h e CY 7C 265 is a 64K R egistered

Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

C2658

Abstract: C2653 C2653 H
Contextual Info: CY7C265 CYPRESS SEMICONDUCTOR Features • CMOS for optimum speed/power • High speed commercial and military — 15 ns max. set-up — 12 ns clock to output • Low power — 660 mW (commercial) — 770 mW (military) • On-chip edge-triggered registers

Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

C2653

Abstract: C2651 C2657 C2658 C2659 C2652 7c26 C2694 C2695 C265
Contextual Info: 1CY 7C26 5 CY7C265 8K x 8 Registered PROM Features If the asynchronous enable E is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW.

SN74V263

Abstract: SN74V263-6 SN74V273 SN74V273-6 SN74V283 SN74V283-6 SN74V293
Contextual Info: SN74V263, SN74V273, SN74V283, SN74V293 8192 x 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 D D D D D D D D D D D Choice of Memory Organizations – SN74V263 – 8192 × 18/16384 × 9

C2657

Abstract: 8193rd
Contextual Info: p vp: v «*1 X X CY7C265 - 8K x 8 Registered PROM Features If the asynchronous enable E is being used, the outputs may be disabled at any tim e by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW.