80960S Search Results

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

VAX-11

Abstract: PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode
Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

v945

Abstract: 80960SA N80960SB W225 80960SB N80960SA S80960SA S80960SB intel DOC n80960
Contextual Info: 80960SA/SB SPECIFICATION UPDATE Release Date: June, 1997 Order Number: 272850-002 The 80960SA/SB may contain design defects or errors known as errata which may cause the 80960SA/SB to deviate from published specifications. Current characterized errata are documented in this Specification Update.

80960SA

Abstract: 80960SB 80960
Contextual Info: Instruction Set g CHAPTER 9 INSTRUCTION SET This chapter provides an overview of the instruction set for the 80960SA/SB processor. Included is a discussion of the instruction format, a summary of the instruction groups and the instructions in each group. This chapter gives detailed descriptions of each of the instructions. The instructions are listed

Intel i960 architecture

Abstract: 80960SA 80960SB A80960SA 80960sa manual
Contextual Info: Guide to This Manual 7 CHAPTER 1 GUIDE TO THIS MANUAL INTRODUCTION This manual provides reference information applicable to the 80960SA/SB embedded processor. It is intended for use by both software and hardware designers fam iliar with the principles of microprocessors and with the 80960SA/SB architecture.

80960SA

Abstract: 80960SB
Contextual Info: Introduction to ¡960 Architecture 2 CH A PTER 2 IN TR O D U C T IO N TO i960™ A R C H ITE C TU R E This chapter provides an overview of the architecture on which the 80960 series o f processors is based. AN EMBEDDED 32-BIT ARCHITECTURE FROM INTEL The 80960SA/SB processor marks the continuation o f the i960 architecture series — an

Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

control unit of a processor

Contextual Info: lACs y7 CHAPTER 11 lACs This chapter describes the intra-agent communication IAC m echanism of the 80960SA/SB processor. Included is a description of the IAC-message structure, the IAC-message sending and receiving mechanism, and reference information on the available IAC messages.

stores procedure

Contextual Info: Procedure Calls 4 CHAPTER 4 PROCEDURE CALLS This chapter describes the 80960SA/SB processor's procedure call and stack mechanism. It also describes the supervisor call mechanism, which provides a means of calling privileged procedures such as kernel services.

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

v945

Abstract: v943 8244 INTEL 80960SA 80960SB N80960SA N80960SB S80960SA W225 intel DOC
Contextual Info: 80960SA/SB SPECIFICATION UPDATE Release Date: August, 2004 Order Number: 272850-003 The 80960SA/SB may contain design defects or errors known as errata which may cause the 80960SA/SB to deviate from published specifications. Current characterized errata are documented in this Specification Update.

Contextual Info: in te i 80960SA/80960SB EMBEDDED 32-BIT PROCESSORS WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS Burst Execution at 16 MHz — 5 MIPS* Sustained Execution at 16 MHz Built-In Interrupt Controller — 4 Direct Interrupt Pins — 32 Priority Levels 256 Vectors

QFP PACKAGE thermal resistance

Abstract: 80960SA 80960SB N80960SB1 65A176 AD928
Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache

80960SB

Contextual Info: Floating-Point Instructions 1Q CHAPTER 10 FLOATING-POINT INSTRUCTIONS This chapter describes the floating-point processing capabilities of the 80960SB processor. The subjects discussed include the real number data types, the execution environment for floating-point operations, the floating-point instructions, and fault and exception handling.

VAX-11

Abstract: 272207
Contextual Info: in t t J P ß m oM ow A nv 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

v945

Abstract: V943 272850 270929-003 80960SA 80960SB N80960SA N80960SB S80960SA S80960SB
Contextual Info: 80960SA/SB SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272850-001 The 80960SA/SB may contain design defects or errors known as errata. Characterized errata that may cause the 80960SA/SB’s behavior to deviate from published specifications are

transistor 778

Abstract: cpu 80960kx printer controller 80960SX Destiny d5001 D8905
Contextual Info: PRINTERS DESTINY TECHNOLOGY CORPORATION D5001 Page Printer Coprocessor • ■ ■ ■ ■ ■ ■ ■ ■ ■ Optimized For Intel i960 Processor Family 80960Sx, 80960Kx, 80960Jx and 80960Cx Supports Up to 1200 dpi Resolutions Band Processing Requires Less

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • ■ ■ High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

80960

Abstract: 74F113 82C54 TL7705A Z8536
Contextual Info: Typical System 73 CHAPTER 13 TYPICAL SYSTEM INTRODUCTION The 80960SA/SB processor and bus have been discussed in previous chapters. All processor systems, in order to have a practical value, must be connected to a memory subsystem and to one or more I/O ports. The memory may take the form of RAM , ROM, magnetic storage or

T7 DIODE

Contextual Info: inttJ PBßyiiflOMÄlHV 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

NFP-32

Contextual Info: Faults 6 CHAPTER 6 FAULTS This chapter describes the fault handling facilities of the 80960SA/SB processor. The subjects covered include the fault-handling data structures, the software support required for fault handling, and the fault handling mechanism. A reference section that contains detailed

advantages of instruction set architecture intel i3

Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • H ig h -P e rfo rm a n c e E m bedded A rc h ite c tu re — 16 M IPS* B u rst E xecution at 16 M H z — 5 M IPS S u stain ed E xecution at 16 M Hz ■ B uilt-in In te rru p t C o n tro lle r