7T7777 Search Results

BI71

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for

KM6865BP-20

Abstract: KM6865BP-15
Contextual Info: KM6865B CMOS SRAM 8 K x 8 Bit High Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Tim e 12 ,15, 20,25ns Max. The KM865B is a 65,536-bit high-speed Static Random • Low Power D issipation Access Memory organized as 8,192 words by 8 bits.

LH21256-12

Abstract: LH21258-15 LH21257-12 LH21256 AE12A lh21257
Contextual Info: LH21256/7/8 FEATURES 262,144 x 1 bit organization Access times: 100/120/150 ns MAX. Cycle times: 200/230/260 ns (MIN.) Page mode operation (LH21256) ^ Nibble mode operation (LH21257) ^ Byte mode operation (LH21258) Power supply: +5 V ± 10% NMOS 256K (256K x 1) Dynamic RAM

800LE

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT _ / I P D 4 2 S 1 7 8 0 0 , 4 2 1 7 8 0 0 16 M BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE D escription TheixPD42S17800, 4217800 are 2,097,152 words by 8 bits CMOS dynamic RAMs. The fast page mode capability realize high speed access and low power consumption.

777T7

Contextual Info: NEC MOS INTEGRATED CIRCUIT / ¿P D 4 2 1 6 4 0 5 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The /iPD4216405 is a 4 194 304 words by 4 bits dynamic CMOS RAM with optional hyper page mode. Hyper page mode is a kind of the page mode and is useful for the read operation.

MPC1490

Abstract: mPD6125ACA PD6125A SE303A-C simple ir remote controll circuit XRL Series 200H AIPD6125ACA-XXX IPD6125AG-XXX 24PIN
Contextual Info: £ * - J . M O S INTEGRATED C IR C U IT PD6125A M U L T I-P U R P O S E REMOTE CO NTRO L T R A N S M IT T E R CMOS IC LSI T he /JP D 6125A is intended fo r ap plicatio ns in infrared re m o te -co n tro l tra n sm itte rs fo r c o n tro llin g T V , VC R ,

A10AL

Abstract: TC538200AFT
Contextual Info: TO SH IB A TC538200AP/AF/AFT TOSHIBA MOS INTEGRATED CIRCUIT SILICON GATE CMOS 8 MBIT 512 K WORD BY 16 BITS/1 M WORD BY 8 BITS CMOS MASK ROM DESCRIPTION The TC538200AP/AF is a 8,388,608-bit Read Only Memory organized as 524,288 words by 16 bits when BYTE is logical high, and as 1,048,576 words by 8 bits when BYTE is logical low.

Contextual Info: IN T E L CORP -CMEMORY/LOGIC} n 4826176 IN TEL CORP M EM O RY/LO G IC i>Ë| LiüHblTfc, O D S ä ^ S 99D 58935 D 29C13 AND 29C14 CHMOS COMBINED SINGLE-CHIP PCM CODEC AND FILTER AT&T D3/D4 and CCITT Compatible 29C14 Asynchronous Clocks, 8th Bit Signaling, Loop Back Test Capability

HM65256BLP-10

Abstract: dp - 20t DG250 HM65256BFP-12T HM65256B HM65256BFP-10T HM65256BFP-15T HM65256BFP-20T HM65256BLFP-10T HM65256BLFP-12T
Contextual Info: HM65256B Series 5.0 V S u p p ly 32,768-w ord x 8-bit H ig h S p e e d P s u e d o S ta tic R A M Features • Single 5 V ±10% • Access time — CE access time: 100/120/150/200 ns — Address access time: 50/60/75/100 ns (in static column mode) • Cycle time

Contextual Info: DATA SHEET \ | F f / MOS INTEGRATED CIRCUIT / juPD42S4210AL, 424210AL 3.3 V OPERATION 4 M BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The Î/PD42S4210AL, 424210AL are 262,144 words by 16 bits CMOS dynamic RAMs with optional hyper page

ltls

Abstract: MARK M2W SI03 256kx4 vram IRFH fscj V52C4258
Contextual Info: JON i 2 '982 V V'TELIC V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512 X 4 SAM HIGH PERFORMANCE V52C4258 80 10 Max. RAS Access Time, tnAC 80 ns 100 ns Max. CAS Access Time, (tcAc) 25 ns 25 ns Max. Column Address Access Time, (t*) 45 ns 50 ns Min. Fast Page Mode Cycle Time, (tPC)

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT MC-422000AA64 2 M-WORD BY 64-BIT DYNAMIC RAM MODULE FAST PAGE MODE Description The MC-422000AA64 is a 2,097,152 words by 64 bits dynamic RAM module on which 8 pieces of 16 M DRAM: JUPD4218160 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.

MS6516L10PC

Abstract: 7T7777 MS6516 MS6516L-10PC MS6516L-10
Contextual Info: MOSEL MS6516 2K x 8 CMOS Static RAM FEATURES DESCRIPTION • Available in 100ns Max. version The MOSEL MS6516 is a high performance, low power CMOS static RAM organized as 2048 words by 8 bits. The device supports easy memory expansion with an active LOW chip enable (E) as well as an active LOW output

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD42S16165L, 4216165L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WOFD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The nPD42S16165L, 42 16165Lare 1 048 576 w o rd s by 16 b its d yn a m ic C MOS R A M s w ith o p tio n a l h yp e r page

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT juPD42S16405L, 4216405L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The mPD42S16405L, 4216405L are 4 194 304 words by 4 bits dynamic CMOS RAMs with optional hyper page mode. Hyper page mode is a kind of page mode and is useful for the read operation.