7C1335 Search Results

7C13

Abstract: CY7C1335
Contextual Info: fax id: 1045 1CY 7C13 35 PRELIMINARY 7C1335 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) The 7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

C133-10

Abstract: C1336 C133-14 CY7C133 CY7C143 IDT7133 IDT7143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

CY7C133

Abstract: CY7C143 IDT7133 IDT7143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

7C13

Abstract: CY7C133 CY7C143 IDT7133 IDT7143 bit-slice C1335
Contextual Info: fax id: 5202 1CY 7C13 3 CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power

MSM 6290

Abstract: msm 5562 27c256 intel 62c512 AP 2068 27C512 microchip 62256 57C256 27C512 SGS-THOMSON 27C512-150
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

CY7C133

Abstract: CY7C143
Contextual Info: CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

EPM5128LC

Abstract: IDT CYPRESS CROSS REFERENCE clocks epm5064lc-1 EPM5128LC-1 EPM5064LC EPM5128LC-2 EPM5128GI EPM5128JC-1 8464c 5962-8871309
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2148-35C CY21L48-35C CY7C168A-35C CY7C168A-25C 5962-8871309XX 5962-89839112X CY2148-35C CY7C148-35C CY7C168A-45M CY7C168A-35M+ 5962-8871310RX 5962-8983913RX CY2148-35M CY7C148-35M CY7C169A-35C

Contextual Info: fax id: 5202 CY7C133 0Y70143 izzazzaar iir ^~-n m n f» o o w r 1 , 1 I n = ~- 2 K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow sim ultaneous reads of the same m em ory location • 2K x 16 organization

Contextual Info: THE FOLLOWING SECOND QUARTER REPORT 1996, the sections entitled “To Our Shareholders” and “Market Perspective” may contain forwardlooking statements about the prospects for Cypress as well as the semiconductor industry more generally including without limitation statements about,

CY7C1335

Abstract: CY7C1336
Contextual Info: 7C1335 CY7C1336 ADVANCED INFORMATION 32K x 32 Synchronous Cache RAM D D D Features D Supports 75ĆMHz Pentiumt and PowerPCt operations with zero wait states D Fully registers inputs and outputs for pipelined operation D D D 32K x 32 common I/O architecture

CY7C1335

Abstract: CY7C1336
Contextual Info: 7C1335 CY7C1336 ADVANCED INFORMATION 32K x 32 Synchronous Cache RAM D D D Features D Supports 75ĆMHz Pentiumt and PowerPCt operations with zero wait states D Fully registers inputs and outputs for pipelined operation D D D 32K x 32 common I/O architecture

CY7C1335

Abstract: CY7C1336 DO30 3Tg 21
Contextual Info: „ ADVANCED INFORMATION 7C1335 CY7C1336 '# C Y P n h b b 32K x 32 Synchronous Cache RAM Features • Synchronous self-timed writes • Supports 75-MHz Pentium and PowerPC™ operations with zero wait states • Asynchronous output enable • JEDEC-standard 100 TQFP pinout

CY7C133

Abstract: CY7C143 IDT7133
Contextual Info: fax id: 5202 —— — Æ j r r ~ 'f V D I 1 CY7C133 CY7C143 D 17 Q Q IT C O O 2K x 16 Dual-Port Static RAM Functional Description Features • True Dual-Ported memory cells which allow simultaneous reads of the same m em ory location • 2K x 16 organization

Contextual Info: fax id: 5202 p vXpX : v « *1 CY7C133 CY7C143 - 2K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells w hich allow sim ultaneous reads of the same m em ory location • 2K x 16 organization • 0.65-micron CMOS fo r optim um speed/power

CY7C133

Abstract: CY7C143 IDT7133 IDT7143 C1338
Contextual Info: 33 CY7C133 CY7C143 2K x 16 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 25/35/55 ns

C1335

Abstract: C1338 TBLA C1333 CY7C133 CY7C143 IDT7133 IDT7143 C1337 CY7C133-35JI
Contextual Info: CY7C133 CY7C143 PRELIMINARY 2K x 16 DualĆPort Static RAM Features D Available in 68Ćpin PLCC D D Pin compatible and functionally equivalent to IDT7133 and IDT7143 D D D D D D D 0.8Ćmicron CMOS for optimum speed/power High speed access: 25 ns greater word widths. It is the solution to

27HC642

Abstract: 39C10B PAL22V10APC CY2254SC-1 7132SA70 93L422AM 7024S15 7130SA25 7C198-45C 7006S
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 2147-35C 7C147-35C 27S03M 54S189M 7C170A-45M 7C170A-35M 2147-45C 2147-35C 27S07AC 7C190-25C 7C171A-35C 7C171A-25C 2147-45C 7C147-45C 27S07AM 7C190-25M 7C171A-45M 7C171A-35M+ 2147-45M+

Contextual Info: 7C1335 32K X 32 Synchronous-Pipelined Cache RAM Features • Supports 1 00-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined oper­ ation • 32K by 32 common I/O architecture • Single 3.3V power supply

CEI 23-16

Abstract: CY7C1329 CY7C1335
Contextual Info: 7C1335 PRELIMINARY 32K X 32 Synchronous-Pipelined Cache RAM Features • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined oper­ ation • 32K by 32 common I/O architecture

Contextual Info: CY7C133 CY7C143 V CYPRESS 2K x 16 Dual-Port Static RAM Features Functional Description True dual-ported m em ory cells which allow sim ultaneous reads of the same mem ory location 2K x 16 organization 0.65-micron CMOS for optimum speed/power High-speed access: 25/35/55 ns

Contextual Info: fax id: 5202 C Y 7 C 1 4 3 CYPRESS C Y 7 C 1 3 3 2K x 16 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 16 organization • 0.65-micron CMOS for optimum speed/power

EPM5128LC

Abstract: EPM5128GC epm5064lc-1 EPM5128LC1 59628867809r 5962-8984106LX EPM5128GI 7C19945DMB EPM5130GC-1 5962-8867812rx
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS 5962-8753903LX 5962-8753902LX CY21L49-55C CY21L49-45C CY7C281 CY7C281A 5962-8863701LX 5962-8753902LX CY6116A-45C CY6116A-35C CY7C286 CY27H512 5962-8867003LX 5962-8867002LX CY6116A-55C CY6116A-45C

84-1MISR4

Abstract: JESD22 MP-8000 "32K x 32" SRAM
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97145 VERSION 1.1 June, 1999 32K x 32 Synchronous Pipelined Cache RAM 7C1335/CY7C1337 CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Reliability Director 408 432-7069 Cypress Semiconductor 32K x 32 Syn. Pipelined Cache RAM