79866 Search Results

AM79865

Abstract: AM79866A
Contextual Info: AMD£I Am79865/79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Fully compliant with ANSI X3T9.5 FDDI, TP-FDDI, and 100BASE-TX/FX PHY standards ■ The on-chip Phase-Locked-Loop PLL only requires an external frequency reference

Contextual Info: DRAWING MA D E T H I S DRAWING C O P Y R IG H T RESERVED . AIMP IN THIRD ANGLE I S UNPUBLISHED. 19 BY AM P P R O D U C T S M AY B E PROJECTION RELEASED FOR PUBLICATIO N IN C O R P O R A T E D , H A R R I S B U R G , P A . CO VERED BY U.S. AND FO R E IG N

AB1205-5

Abstract: DP83223
Contextual Info: AB-1205-5 4 Port Cascadeable 100base and ATM Repeater Hub AB-1205-5 4-Port 100baseTX Repeater Product Specification AB Semicon AB1205-5 100base and ATM Repeater Hub Product Specification Copyright Copyright 1997 AB Semicon Limited. All rights reserved. No part of this

TCFR10

Abstract: 44-PIN MC68836 ML6673 ML6691 MDIO MDC
Contextual Info: March 1997 ML6691* 100BASE-T MII-to-PMD Transceiver GENERAL DESCRIPTION FEATURES The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 100BASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/ decoder, a Stream Cipher scrambler/descrambler, and

Syntek Semiconductor 1261

Abstract: Nam Tai Electronics Es325 syntek Dynatek 110
Contextual Info: LG Semicon SALES NETWORK OVERSEAS SUBSIDIARIES & OFFICES U.SJV LG Semicon America, Inc. 3003 North First Street San Jose, CA 95134-2004 Tel : 1 408-432-5000 Fax : (1)408-432-6067 LGSA Raleigh Office 5511 Capital Center Drive, Suite 430, Raleigh, NC 27606

Contextual Info: FINAL AMDZ1 Am79865/79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Fully compliant with ANSI X3T9.5 FDDI, TP-FDDI, and 100BASE-TX/FX PHY standards ■ The on-chip Phase-Locked-Loop PLL only requires an external frequency reference

Contextual Info: FINAL AMD£I Am79865/79866A Physical DataTransmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Fully compliant with ANSI X3T9.5 FDDI, TP-FDDI, and 100BASE-TX/FX PHY standards ■ The on-chip Phase-Locked-Loop PLL only requires an external frequency reference

Contextual Info: June 1995 PRELIMINARY ^ÉkMicro Linear ML6691 100BASE-T MIl-to-PMD Transceiver GENERAL DESCRIPTION FEATURES The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 10OBASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/

1025460

Abstract: 7805 UA1044 UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160
Contextual Info: Features • • • • • • • • • • • • • • • • • High performance ULC family suitable for large-sized CPLDs and FPGAs Conversion to 1,000,000 gates Pin counts to over 976 pins Any pin–out matched due to limited number of dedicated pads

AM78965

Abstract: pal16v8 extcrs2
Contextual Info: Ü Ü !Ï • W iJ I U MX98741 1.0 XRC 100 BASE-TX/FX Repeater Controller Features • 208-pin, C M O S device in PQFP package • Eight 100 B A S E -TX /FX ports; each port individually configurable to T X or FX • Direct interface with analog clock generation/recovery chips

ME6691

Contextual Info: March 1997 % M i c r o Linear ML6691 100BASE-T M II-to-PM D Transceiver GENERAL DESCRIPTION FEATURES The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 1OOBASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/

rsm ah 16

Abstract: 0224a ic Accessible Local code
Contextual Info: mÉL Micro June 1995 PRELIMINARY Linear ML6691 100BASE-T MII-to-PMD Transceiver G EN ERA L D ESCR IPTIO N FEATURES The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 100BASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/

sem 3040 ic

Abstract: 941 LG
Contextual Info: SALES NETWORK LG Semicon OVERSEAS SUBSIDIARIES & OFFICES U.S.A L G S e m ic o n A m e r ic a , Inc. 3 0 0 3 North F irs t S tre e t S a n Jo s e , C A 9 5 1 3 4 -2 0 0 4 T e l : 1 408 -43 2-50 00 F a x : (1)408 -43 2-60 67 LGSA Raleigh Office 5511 Capital Center Drive,

Contextual Info: March 1997 ML6691 100BASE-T MII-to-PMD Transceiver GENERAL DESCRIPTION FEATURES The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 100BASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/ decoder, a Stream Cipher scrambler/descrambler, and

5PDT

Abstract: AM79866 79866 AM79865
Contextual Info: H Preliminary Am79865/79866 Advanced Micro Devices Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Parallel Input to the PDT Is a 5-bit encoded NRZ symbol clocked by LSCLK Parallel output from the PDR Is a 5-bit

AM79865

Abstract: AM79866A
Contextual Info: A M D ii Am79865/79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Fully compliant with ANSI X3T9.5 FDDI, TP-FDDI, and 10OBASE-TX/FX PHY standards ■ The on-chip Phase-Locked-Loop PLL only requires an external frequency reference

sem 3040

Abstract: 44022 ee ca 3161 e IC
Contextual Info: SALES NETWORK LG Semicon OVERSEAS SUBSIDIARIES & OFFICES U.S.A LG Semicon America, Inc. 3003 North First Street San Jose, CA 95134-2004 Tel : 1 408-432-5000 Fax : (1)408-432-6067 LGSA Raleigh Office 5511 Capital Center Drive, Suite 430, Raleigh, NC 27606

75017

Contextual Info: Mpact media processor Family_ LG Semicon OVERSEAS OFFICES U.S.A LG Semicon America Inc. 3003 North First Street San Jose, CA 95134-2004 Tel . 1 408-432-5000 Fax : (1 )408-432-6067 HONG KONG LG Semicon(H.K.) Ltd. Rm 1602,16F., Bank of America Tower

Contextual Info: UA1 Series 0.35 µm ULC Series Description The UA1 series of ULCs is well suited for conversion large sized CPLDs and FPGAs. Devices are implemented in high–performance CMOS technology with 0.35–µ m drawn channel lengths, and are capable of supporting

Contextual Info: US890 0 / US891 Two-Coil Fan Driver – High Ou utput Current Features and Benefits Application Example es Peak output current up to 1200mA A Low start-up voltage Low output resistance High sensitivity integrated Hall Se ensor Power-efficient CMOS and power

Contextual Info: a P R E L IM IN A R Y Advanced Micro Devices Am79865/79866A Physical Data Transmitter/Physical Data Receiver DISTINCTIVE CHARACTERISTICS • Parallel Input to the PDT is a 5-blt encoded NRZ symbol clocked by LSCLK 125 MBaud 100 Mbps serial link data rate

PQR168

Abstract: Am79C830A CGX169 4570 pin out diagram LG plc plc lg FDD11994 PQR120 15502C
Contextual Info: AMD a Am 79C830A FORMAC Plus CGX169 169-Lead Pin Grid Array Without H eat Sink measured in inches Physical Dimensions 6-3 i l AMD Am 79C830A FORMAC Plus PQR168 168-Pin Plastic Quad FlatPack (Trimmed and Formed) (measured in inches) TOP VIEW 6-4 The SUPERNET 2 Family for FDD11994 Data Book

UA1044

Abstract: UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160 UA1184 UA1208
Contextual Info: UA1 Series 0.35 µm ULC Series Description The UA1 series of ULCs is well suited for conversion large sized CPLDs and FPGAs. Devices are implemented in high–performance CMOS technology with 0.35–µ m drawn channel lengths, and are capable of supporting

Contextual Info: March 1997 % M ic r o L in e a r ML6691 100BASE-T MII-to-PMD Transceiver GENERAL DESCRIPTION FEATURES The ML6691 implements the upper portion of the physical layer for the Fast Ethernet 100BASE-T standard. Functions contained in the ML6691 include a 4B/5B encoder/