780NS Search Results

Contextual Info: HARRIS SEMICOND SECTOR bûE D • 43D2271 GÜSGS1S n i HHAS HGTG20N120E2 34A, 1200V N-Channel IGBT Decem ber 1993 Package Features JEDEC STYLE TO-247 TOP VIP N • 34 Amp, 1200 Volt • Latch Free Operation • Typical Fall Time - 780ns t COLLECTOR BOTTOM SIDE

TA49009

Contextual Info: HGTG20N120E2 34A, 1200V N-Channel IGBT December 1993 Package Features • JEDEC STYLE TO-247 TOP VIEW 34 Amp, 1200 Volt • Latch Free Operation • Typical Fall Time - 780ns • High Input Impedance i COLLECTOR • Low Conduction Loss Description The HGTG20N120E2 is a MOS gated, high voltage switch­

G20N120E2

Abstract: AN7254 AN7260 HGTG20N120E2 LD26 HGTG
Contextual Info: HGTG20N120E2 S E M I C O N D U C T O R 34A, 1200V N-Channel IGBT April 1995 Features Package JEDEC STYLE TO-247 • 34A, 1200V • Latch Free Operation EMITTER • Typical Fall Time - 780ns COLLECTOR GATE • High Input Impedance COLLECTOR BOTTOM SIDE METAL

G20N120E2

Abstract: AN7254 AN7260 HGTG20N120E2 LD26
Contextual Info: HGTG20N120E2 Semiconductor 34A, 1200V N-Channel IGBT April 1995 Features Package JEDEC STYLE TO-247 • 34A, 1200V • Latch Free Operation EMITTER • Typical Fall Time - 780ns COLLECTOR GATE • High Input Impedance COLLECTOR BOTTOM SIDE METAL • Low Conduction Loss

Contextual Info: Q l ILC DATA DEVICE BUS-65153 CORPORATION _ _ 0 9 19» MIL-STD-1553B, NOTICE 2 & MIL-STD-1760A STIC" - SMALL TERMINAL INTERFACE CIRCUIT FEA TU R ES DESCRIPTION The BUS-65153 is a complete, dual redundant MIL-STD-1553B Remote Terminal. Packaged in a 1.90 x 1.0x0.2",

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

Contextual Info: B U R R -B R O W N r a s ADS602 i 12-Bit 1MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • • • • • DIGITAL SIGNAL PROCESSING • HIGH-SPEED DATA ACQUISITION SYSTEMS • MEDICAL INSTRUMENTATION • ANALYTICAL INSTRUMENTATION LOW LINEARITY ERROR

A17-A14

Contextual Info: W89C940 yfTTPX S S S S S S S S S S S S S S S S S S S S S S S S S S \\\\\\ E ¡ecirosri ic s C o rp . ELANC-PCI TWISTED-PAIR ETHER-LAN CONTROLLER WITH

Contextual Info: B T 3Æ ADS-930 T O . 16-Bit, 500kHz Sampling A/D Converters IN N O V A TIO N a n d E X C E L L E N C E FEATURES • 1 6 - B lt r e s o lu t io n • 5 0 0 k H z s a m p lin g r a te • F u n c tio n a lly c o m p le t e • E x c e lle n t d y n a m ic p e r f o r m a n c e

Contextual Info: W89C940 ELANC-PCI TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE GENERAL DESCRIPTION he ELANC-PCI (Twisted-pair Ether-LAN Controller with PCI Interface) integrates a W89C902 Serial(ELANCPCI) LAN Coprocessor for Twisted-Pair (SLCT) and PC/AT PCI bus interface logic into a single chip. The

H355LDK-8281

Abstract: TH355LSK G355ENK-8282 2.3MHz 2.8MHz TH355LNK-4550 4MHz LC Band Pass Filter TOKO 27mhz TOKO LC Filter 4fw toko toko filter LC
Contextual Info: TOKO LC Filters for TV, VCR and Video Camera TYPE 4FW TYPE 4FW Features l Ultra-compact LC block filters based on 4mm square coil units. Suitable for surface mounting. l Basic units will take up to 2 built-in capacitors. l Adjustable and non-adjustable types available. Up to three

ISA CODE VHDL

Abstract: 16x4 ram VERILOG IPUG35
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.3, January 2009 LatticeXP2 Family Handbook Table of Contents January 2009 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

CL680 C-Cube

Abstract: CL680 0x246
Contextual Info: 16 CL680 DRAM Configuration Reference This chapter describes the DRAM configuration reference, a collection of locations in local DRAM that the host may use to monitor and configure the operation of the CL680VCD and CL680CD-G modules. Note: Newer releases of microcode may contain values which differ from this chapter.

LFXP2-5E-5QN208C

Abstract: ld33 LFXP2-5E-5M132C XP2 LFXP2-5E-5QN208C LD33 F LFXP2-5E lfxp2-8E lattice xp2 LFXP2-8E-5QN208C IPUG35
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.4, May 2009 LatticeXP2 Family Handbook Table of Contents May 2009 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

2S*1206

Abstract: 2S1201 2S1204 2SJ224 2SJ214LS 2s1208 2S1209 2SJ200 2SJ214 2SJ201
Contextual Info: - 24 - « tt m £ & m m f t ? 1 * K jç. H V m * £ (V) * * P d /P c h (A) % m Í& * * (W) I gss (max) (A) Vg s (V) 0*3 (min) (max) Vd s (A) (A) (V) (Ta=25Xl) (min) (max) Vd s (V) (V) (V) Id (A) (min) (S) Vd s {\ l f (V) 1d (A) 2SJ200 LF PA MOS P E -180 DSS

Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

diode 930 b14

Abstract: 22MF 33PF 74HCT 74HCT373 74HCT86 ADS-930 ADS-930MC ADS-930MM P1-11
Contextual Info: www.murata-ps.com ADS-930 16-Bit, 500kHz Sampling A/D Converters PRODUCT OVERVIEW The low-cost ADS-930 is a high-performance, 16-bit, 500kHz sampling A/D converter. This device accurately samples fullscale input signals up to Nyquist frequencies with no missing codes. The

02A4

Abstract: A001 XP2-17 single port RAM
Contextual Info: LatticeXP2 Memory Usage Guide November 2008 Technical Note TN1137 Introduction This technical note discusses memory usage for the LatticeXP2 device family. It is intended to be used by design engineers as a guide for integrating the User TAG, EBR- Embedded Block RAM and PFU-based memories in this

MTC27

Abstract: 2x4 TTL demultiplexer 106 35K 045 226 35K AU-AIS Digital Alarm Clock by using ttl MTB 230 P03H GR-253-CORE IXF6151
Contextual Info: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.

74as574

Contextual Info: 12-Bit 1MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • • • • • DIGITAL SIGNAL PROCESSING • HIGH-SPEED DATA ACQUISITION SYSTEMS • MEDICAL INSTRUMENTATION • ANALYTICAL INSTRUMENTATION • TEST AND IMAGING SYSTEMS • WAVEFORM ANALYZERS

Contextual Info: Q ADS602 Or, Call Customer Service at 1•800-548-6132 USA Only FEATURES APPLICATIONS • • • • • DIGITAL SIGNAL PROCESSING • HIGH-SPEED DATA ACQUISITION SYSTEMS • MEDICAL INSTRUMENTATION • ANALYTICAL INSTRUMENTATION • TEST AND IMAGING SYSTEMS

LFXP2_8E_5FT256C

Abstract: ld33 LD33 V LD33 e LD41 lfxp2-8E LFXP2-8E-6FT256C verilog code for correlator LVCMOS25 3 tap fir filter based on mac vhdl code
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.5, February 2010 LatticeXP2 Family Handbook Table of Contents February 2010 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

0226D

Contextual Info: ® ADS-930 16-Bit, 500kHz Sampling A/D Converters INNOVATION and EXCELLENCE FEATURES • • • • • • • • • 16-bit resolution 500kHz sampling rate Functionally complete Excellent dynamic performance 83dB SNR, –89dB THD No missing codes Small 40-pin TDIP package

Contextual Info: LatticeXP2 Family Handbook HB1004 Version 01.7, April 2008 LatticeXP2 Family Handbook Table of Contents April 2008 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1