77MHZ Search Results

74hc74a

Abstract: plj1 TC74HC74
Contextual Info: - TC74HC74AP/AF/AFN D U A L D - T Y P E F L I P FLOP PRESET A N D C L EA R T h e T C 74H C 74A is a h ig h spe ed CM O S D F L I P F L O P f a b r i c a t e d w i t h s i l i c o n g a t e C 2M O S t e c h n o l o g y . I t a c h i e v e s t h e h i g h s p e e d o p e r a t i o n s i m i l a r to

Contextual Info: SEMICONDUCTOR TECHNICAL DATA KIC7W74FU SILICON MONOLITHIC CMOS DIGITAL INTEGRATED CIRCUIT D-TYPE FLIP FLOP WITH PRESET AND CLEAR The KIC7W74FU is a high speed C2MOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

Contextual Info: THC63LVD827_Rev.1.00_E THC63LVD827 LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER General Description Features The THC63LVD827 transmitter is designed to support pixel data transmission between Host and Flat Panel Display and Dual Link transmission between Host and

Contextual Info: 2: 59 AM TUPP 2488 ASSP Telecom Standard Product Data Sheet Released ay ,1 8N ov em TUPP™ 2488 be r, 20 04 03 :5 PM5364 Data Sheet Released Issue No. 7: August 2004 Do wn l oa de d by C on te n tT ea m of Pa r tm in er In co n Th ur sd SONET/SDH Tributary Unit Payload

Contextual Info: Spec Sheet INDUCTORS High Reliability Application SMD Power Inductors for Industrial / Automotive Comfort and Safeｔｙ Applications (NR series H type / V type / S type) NRS6010T1R5MMGFV Features Item Summary 1.5 H(±20%), 2400mA, 1900mA Lifecycle Stage

Contextual Info: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge PROGRAMMABLE CLOCK DIVIDER/FANOUT SY89871U BUFFER WITH INTERNAL TERMINATION Final FEATURES DESCRIPTION • Two matched-delay outputs: • Bank A: undivided pass-through QA • Bank B: programmable divide by

Contextual Info: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge SY89874U PROGRAMMABLE CLOCK DIVIDER/FANOUT Final BUFFER WITH INTERNAL TERMINATION FEATURES DESCRIPTION • Integrated programmable clock divider and 1:2 fanout buffer ■ Guaranteed AC performance over temperature and

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT /¿PD4516421, 4516821, 4516161 16M-bit Synchronous DRAM D escrip tio n The /iPD4516421, 4516821, 4516161 are high-speed 16,777,216-bit synchronous dynam ic random-access m em ories, organized as 2,097,152x4x2, 1,048,576x8x2 and 524,288x16x2 w ordxbitxbank , respectively.

dual port fifo

Contextual Info: 6000 Family Architectural Description available as dedicated device outputs. These signals are also available as inputs to the GRP to facilitate use by onchip logic. ispLSI 6000 Family Introduction The ispLSI 6192 is a high-density, Cell-Based programmable logic device containing a dedicated Memory

verilog code for BPSK

Abstract: verilog code for 2D linear convolution filtering verilog code for discrete linear convolution ep330 PLMQ7192/256-160NC convolution Filter verilog HDL code AN-084 EPC1PC8 EPM7160 Transition verilog code image processing filtering
Contextual Info: Newsletter for Altera Customers ◆ Second Quarter ◆ May 1997 Altera Announces MAX Roadmap with 3.3-V, ISP-Capable Michelangelo Family Altera recently unveiled plans for the next-generation MAX programmable logic device PLD family, code-named Michelangelo.

A03 SMD

Abstract: smd code n03 smd p08 t06 smd T14 N03 OSAD14 smd code t04 smd code t06 b09 n03 SMD11
Contextual Info: CS22250 Data Sheet Wireless 10BT Controller 1 Introduction The Cirrus Logic CS22250 Wireless Network Controller enables high speed, 11 Mbps digital wireless data connectivity for wireless Ethernet bridge, access points, and other broadband applications. The CS22250 is a highly integrated single-chip Ethernet bridge solution for wireless networks

TJ-105

Abstract: Cypress 1990
Contextual Info: 11 AM FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet Released be r, 20 04 02 :2 2: PM7311 ay ,0 4N ov em FREEDM 84A1024L Data Sheet Released Issue 2: Do wn l oa de d by C on te n tT ea m of Pa r tm in er In co n Th ur sd Frame Engine and Data Link Manager

OCDS1

Contextual Info: 16 AM PM2329 ClassiPI Network Classification Processor Datasheet eb 8F Fr id ay ,1 ClassiPI ru ar y, 20 05 12 :4 1: PM2329 Datasheet oa de d by C on te n tT ea m of Pa rtm in er In co n Network Classification Processor Proprietary and Confidential Issue 4, November 2001

Contextual Info: 9: 25 PM FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet Released 9M ay ,2 00 5 11 :2 PM7312 Mo nd ay ,0 FREEDM 32A1024L tis h d of ag er rt on Frame Engine and Data Link Manager 32A1024L Do wn lo ad ed by sa Data Sheet Released Issue 2: Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.

Contextual Info: Voltage Controlled Crystal Oscillator VCXO TCO-2152 Series 7x5 VCXO Application Features Measurement system Transmission equipment High frequency Wide frequency control range With Tri-state Specifications Type TCO-2152 Standard Frequency 155.52 MHz Supply voltage

B0J0

Abstract: LAVDH msu1 12-2 PMC-2021098
Contextual Info: 5: 03 AM TUPP 2488 ASSP Telecom Standard Product Data Sheet Released es da y, 09 Oc to TUPP™ 2488 be r, 20 07 04 :2 PM5364 Data Sheet Released Issue No. 7: August 2004 Do wn lo ad ed by IH S Pa r ts Ma na g em en tI nc .o fI HS IN C on Tu SONET/SDH Tributary Unit Payload

Contextual Info: 6000 Family Architectural Description available as dedicated device outputs. These signals are also available as inputs to the GRP to facilitate use by onchip logic. ispLSI and pLSI 6000 Family Introduction The ispLSI and pLSI® 6192 devices are high-density,

Contextual Info: Precision Edge 2.5GHz ANY DIFF. IN-TO-LVPECL ® SY89871U Precision Edge PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION Micrel, Inc. FEATURES Precision Edge® ̈ Two matched-delay outputs: • Bank A: undivided pass-through QA

BAT 98

Contextual Info: HA RR IS SE MI C O N D SECT OR L.AE D • 43 02 27 1 0 0 50 71 7 S7T ■ m harfiis HAS HA-2557 SEMICONDUCTOR f MM M . 4L* # Wideband Four Quadrant Current Output Analog Multiplier February 1994 Features Description • Low Multiplication Error.1.5%

Contextual Info: 2.5GHz ANY DIFF. IN-TO-LVPECL Precision Edge SY89874U PROGRAMMABLE CLOCK DIVIDER/FANOUT FINAL BUFFER WITH INTERNAL TERMINATION FEATURES • Integrated programmable clock divider and 1:2 fanout buffer ■ Guaranteed AC performance over temperature and voltage:

Contextual Info: TOSHIBA TC74HC374AP/AF/AFW TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC374AP, TC74HC374AF, TC74HC374AFW Note The JEDEC SOP (FW ) is not available OCTAL D-TYPE FLIP-FLOP WITH 3 - STATE OUTPUT in Japan The TC74HC374A is a high speed CMOS OCTAL FLIPFLOP with 3 - STATE OUTPUT fabricated with silicon gate

lattice 1996

Contextual Info: Specifications ispLSI and pLSI 6192 ® ispLSI and pLSI 6192 High Density Programmable Logic with Dedicated Memory and Register/Counter Modules — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design Copying Features • A FAMILY OF HIGHLY INTEGRATED, CELL-BASED,