74LVC3G Search Results

MARKING V7 6-PIN

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

74LVC3G14

Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74LVC3G07

Abstract: 74LVC3G07DC 74LVC3G07DP 74LVC3G07GM 74LVC3G07GT
Contextual Info: 74LVC3G07 Triple buffer with open-drain output Rev. 7 — 9 August 2010 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Contextual Info: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC3GU04 Triple inverter Rev. 10 — 6 July 2012 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 12 — 9 April 2013 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

MO-187

Abstract: 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E
Contextual Info: 74LVC3G04 Triple inverter Rev. 05 — 5 October 2007 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC3G04 Triple inverter Preliminary specification File under Integrated Circuits, IC24 2003 Aug 19 Philips Semiconductors Preliminary specification Triple inverter 74LVC3G04 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 5.5 V

mnb120

Contextual Info: 74LVC3GU04 Triple inverter Rev. 01 — 12 May 2004 Product data sheet 1. General description The 74LVC3GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these

Contextual Info: 74LVC3G34 Triple buffer gate Rev. 01 — 29 April 2004 Product data sheet 1. General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74LVC3G17

Abstract: 74LVC3G17DC 74LVC3G17DP 74LVC3G17GM 74LVC3G17GT JESD22-A114E MO-187
Contextual Info: 74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 05 — 13 March 2008 Product data sheet 1. General description The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free

74LVC3GU04

Abstract: 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT JESD22-A114E MO-187 VU04
Contextual Info: 74LVC3GU04 Triple inverter Rev. 06 — 4 March 2008 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of

74LVC3G06

Abstract: 74LVC3G06DC 74LVC3G06DP 74LVC3G06GM 74LVC3G06GT JESD22-A114E MO-187
Contextual Info: 74LVC3G06 Triple inverter with open-drain output Rev. 07 — 12 March 2009 Product data sheet 1. General description The 74LVC3G06 provides three inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

74LVC3G04

Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187
Contextual Info: 74LVC3G04 Triple inverter Rev. 07 — 16 June 2008 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

74LVC3G34

Abstract: 74LVC3G34DC 74LVC3G34DP 74LVC3G34GD 74LVC3G34GM 74LVC3G34GT
Contextual Info: 74LVC3G34 Triple buffer Rev. 8 — 2 September 2010 Product data sheet 1. General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment.

74LVC3G06

Abstract: 74LVC3G06DC 74LVC3G06DP 74LVC3G06GT MO-187 1.4541
Contextual Info: 74LVC3G06 Triple inverter with open-drain output Rev. 03 — 01 February 2005 Product data sheet 1. General description The 74LVC3G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Contextual Info: 74LVC3G06 Triple inverter with open-drain output Rev. 10 — 27 June 2012 Product data sheet 1. General description The 74LVC3G06 provides three inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Contextual Info: 74LVC3GU04 Triple inverter Rev. 9 — 23 November 2011 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of

Contextual Info: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 8 — 21 September 2011 Product data sheet 1. General description The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free

Contextual Info: 74LVC3G07 Triple buffer with open-drain output Rev. 11 — 9 April 2013 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Contextual Info: 74LVC3GU04 Triple unbuffered inverter Rev. 11 — 9 April 2013 Product data sheet 1. General description The 74LVC3GU04 is a triple unbuffered inverter. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC3G04 Triple inverter Rev. 11 — 2 April 2013 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC3G07 Triple buffer with open-drain output Rev. 8 — 19 October 2011 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.