74LS8 Search Results

001-04

Contextual Info: fita SANYO SEMICONDUCTOR CORP 7 cili707b 0010401 HIT B H S A J S3E D -T-HZ- 2 / Ko.3629 MLC74HC86 CMOS High-Speed Standard Logic Quad 2-Input EX-OR Gate Features •The MLC74HC86 consists of 4 identical 2-input exclusive-OR gates. ■Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL 74LS86

74LS348

Abstract: G104 74LS848 LS348 SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS348 SN54/74LS848 8-INPUT PRIORITY ENCODERS WITH 3-STATE OUTPUTS The SN54 / 74LS348 and the SN54 / 74LS848 are eight input priority encoders which provide the 8-line to 3-line function. The outputs A0 – A2 and inputs (0 – 7) are active low. The active low input

TTL 7486

Abstract: 74 LS 00 Logic Gates 7486 TTL 74LS86 TTL ls 7486 TTL 7486 AND propagation delay
Contextual Info: Signetics I 7486, LS86, S8Ó Gates Quad Two-Input Exclusive-OR Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 7486 14ns 30mA 74LS86 10ns 6.1mA 74S86 7ns 50mA ORDERING CODE COMMERCIAL RANGE V cc = 5 V + 5 % ; T a = 0°C to +70°C

N74S89N

Abstract: N74LS89F N74LS89N N74S89F S54LS89F S54S89F
Contextual Info: 54S/74S89 54LS/74LS89 Preliminary LOGIC SYMBOL data FEATURES DESCRIPTION T h e ''S S }" is a 6 4 -B it h ig h -s p e e d R e a d / W r it e R a n d o m A c c e s s M e m o r y fo r u s e a s a “s c r a t c h p a d 1’ m e m ory with n o n -d e stru c tiv e

74LS86p

Abstract: M74LS86P
Contextual Info: M IT S U B IS H I LSTTLs M 74LS86P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATES DESCRIPTION The M 7 4L S 86 P is a semiconductor integrated PIN CONFIGURATION TOP VIEW circuit containing 4 dual-input exclusive-OR gates. FEATURES • , High breakdown input voltage (V | i 1 5 V )

74LS348

Abstract: LS348
Contextual Info: 8 MOTOROLA DESCRIPTION - The SN54LS/74LS348 and the SN54LS/74LS848 are eight input priority encoders which provide the 8-line to 3-line function. The outputs(A0-A2) and inputs (0-7) are active low. The active low input which has the highest priority {input 7 has the highest) is represented on the

74LS83AP

Contextual Info: g M O TO R O LA , SN54/74LS83A D E SC R IP T IO N — The S N 5 4 L S /7 4 L S 8 3 A is a high-speed 4 -B it Binary F u ll A dder w ith internal carry lookahead. It accepts tw o 4-bit binary w ord s — A 4 , 8 i — B 4 )and a Carry Input (Co).lt generates the binary

Contextual Info: I LS TTL DN74LS Series 74LS83A 74LS83A 4 - bit Binary F u ll Adders with F a st Carry • Description P -2 DN 74LS83A is a 4-bit full-adder w ith a “look-ahead” carry. ■ • • • Features “ Look-ahead” carry for high speed Partial “look-ahead” carry for system capability

ic 74ls86

Abstract: 74LS86 pin configuration ic
Contextual Info: GD54/74LS86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES Description Pin Configuration This device contains four independent 2-input Exclusive-OR gates. It performs the Boolean func­ tions Y = A B = A B + A B in positive logic. 1 1A 2 1B 3 1V 4 5 6 7 2A 2B 2Y

74LS86PC

Abstract: 74LS86p 7486 pinout 7486PC pin diagram of 7486 74S86PC 74LS86 gate diagram t3d7 diode 74LS86 74ls86 pin diagram
Contextual Info: 86 CONNECTION DIAGRAM PINOUT A vè4/7486 £,^ ò ~7 / ^S4S/74S86 O f l ù V54LS/74LS86 o / / b i < j QUAD 2-IN PU T EXCLUSIVE-OR GATE ORDERING CODE: See Section 9 PIN PKGS O UT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%,

ttl ic 7485

Contextual Info: SN548S, SNS4LS85, SN54S85 SN7485, 74LS85, SM74S85 4-BIT MAGNITUDE COMPARATORS MARCH 1974 - REV ISEO M ARCH 1988 TYPE TYPICAL POWER DISSIPATION TYPICAL DELAY 4-BIT WORDS SN 5485, SN 54LS85, SN 54S86 . . . J OR W PACKAGE SN 7485 . . . N PACKAGE SN 74LS85, SN 74S85 . . . D OR N PACKAGE

74LS83AP

Abstract: 7483AP 7483APC 74LS83APC 54LS83ADM 74LS83ADC 7483 5483ADM 5483AFM 54LS83AFM
Contextual Info: 83A CONNECTION DIAGRAM PINOUT A o / &I ^ ’ ‘ 54LS/74LS83A Ï 4-BIT BINARY FULL ADDER W ith Fast Carry / a3|T Të] S3 s2(T Ts] s3 a 2[7 Î4|C< b2 T3] Co [7 12] GND vcc [ I Si T I bo [7 TÖ1 Ao Ai [S "9] So B, DESCRIPTION — The ’83A high speed 4-bit binary fu ll adders w ith internal

7486PC

Abstract: 74LS86PC
Contextual Info: 86 CONNECTION DIAGRAM PINOUT A v£4/7486 J/S4S/74S86 0 / / ^ 7 6 V54LS/74LS86 o / / 1 1 < - { QUAD 2-INPUT EXCLUSIVE-OR GATE ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70°C Vcc = +5.0 V ±10%,

74LS86

Abstract: TTL 74ls86 truth table NOT gate 74 74LS86 ttl truth table and gate 74 74LS86 truth table truth table OR gate 74 751A-02 4 inputs OR gate truth table 5 inputs OR gate truth table
Contextual Info: SN54/74LS86 QUAD 2-INPUT EXCLUSIVE OR GATE QUAD 2-INPUT EXCLUSIVE OR GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 1 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 TRUTH TABLE IN OUT A B Z L L H H L H L H L H H L 14 1

74LS83AP

Abstract: M74LS83AP
Contextual Info: MITSUBISHI LSTTLs M 74LS83A P 4 -B IT B IN A R Y FULL ADDER W IT H FAST CARRY DESCRIPTION The M 74LS83A P PIN CONFIGURATION TOP VIEW is a sem ico n d u c to r in teg rated c irc u it c o n ta in in g a 4 -b it b in a ry lo o k ahead carry ty p e fu ll adder.

54HC

Abstract: 54LS85 74HC 74LS85 C1995 MM54HC85 MM54HC85J MM74HC85 MM74HC85J truth table for 4 bit magnitude comparator
Contextual Info: MM54HC85 MM74HC85 4-Bit Magnitude Comparator General Description The comparator’s outputs can drive 10 low power Schottky TTL LS-TTL equivalent loads and is functionally and pin equivalent to the 54LS85 74LS85 All inputs are protected from damage due to static discharge by diodes to VCC and

Contextual Info: LS TTL DN74LS Series 74LS86 74LS86 Quad 2 -input Exclusive OR Gates • Description P-1 D N 74LS86 contains four 2-input exclusive O R gate circuits. ■ • • • • Features Low pow er consum ption P d = 30.5m V typical High speed ( t pd = 10ns typical)

DN74LS86

Abstract: VM48
Contextual Info: I 74LS86 LS TTL DN74LS Series 74LS86 Quad 2 -input Exclusive OR Gates • P-1 Description DN 74LS86 contains four 2-input exclusive O R gate circuits. ■ • • • • Features Low pow er consum ption P<j = 30.5m V typical High speed ( t p(i = 10ns typical)

5489DM

Abstract: 5489FM 54LS89DM 7489DC 7489FC 7489PC 74LS89DC 74LS89FC 74LS89PC 74LS89
Contextual Info: 89 C O N N E C T IO N D IA G R A M P IN O U T A 54 /7489 ^ V54LS/74LS89 ¿>//7f<? 6 4 -B IT R A N D O M A C C E S S M EM O R Y W ith O p e n -C o lle c to r O utputs D E S C R IP T IO N — T h e ’89 a high speed, lo w p o w e r 6 4 -b it R andom A cce ss

TTL 7486

Abstract: 74LS86 pin configuration N74LS86N 7486 signetics 74ls ttl 132 74ls86 74LS 74S86 LS86 N7486N
Contextual Info: Signelics I 7486, LS86, S86 Gates Quad T w o-Inp ut Exclusive-OR Gate Product Specification L o gic P roducts TY PE T Y P IC A L P R O P A G A TIO N DELAY T Y P IC A L SU P P LY C U R R E N T T O T A L 7486 14ns 30m A 74LS86 10ns 6.1m A 74S 86 7ns 50m A

74LS86 gate diagram

Abstract: TTL 74ls86 pin diagram of 74ls86 LC74HC86M 74LS86 cmos 74ls86 LC74HC86 74LS series logic gates 3 input or gate 74ls86 pin diagram diode I-35 L
Contextual Info: SANYO SEMICONDUCTOR COUP LEE D i 7m Q 7\n DDDSbTa 7 T -V 3 -^ / LC74HC86M* t C M O S High-Speed Standard Logic LC 74H C Series 3034A Quad 2-Input Exclusive OR Gate 2187. , Features • The LC74HC86M consists of 4 identical 2-input exctusive-OR gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to LS-TTL 74LS86 w ith the low

pin diagram of ic 74ls85

Abstract: 74LS85 IC - 74LS85 IC 74LS85 74LS85 ttl of ic 74ls85 74LS8B 74lsb5
Contextual Info: g M O T O R O LA SN54 / 74 LS85 D E S C R IP T IO N — The S N 54LS/74LS85 is a 4-Bit Magnitude Compar­ ator which compares two 4-bit words (A, B), each word having four Parallel Inputs <Ao-A3, 8 0-8 3 ); A 3 ,8 3 being the most significant inputs. Operation is not restricted to binary codes, the device will work with any

74LS84

Contextual Info: M <8> O T O R O L A SN54/74LS348 D ESCRIPTIO N — The SN54LS/74LS348 and the SN54LS/74LS848 are eight input priority encoders which provide the 8-line to 3-line function. The outputs A0-A2 and inputs (0-7) are active low. The active low input which has the highest priority(input 7 hasthehighest) Is represented on the

74LS85

Abstract: truth table for 4 bit magnitude comparator 4 bit magnitude comparator 74ls85 74ls85 datasheet schottky B22 OA 70 diode 4 bit magnitude comparator OA 10 diode
Contextual Info: SN54/74LS85 4-BIT MAGNITUDE COMPARATOR The SN54 / 74LS85 is a 4-Bit Magnitude Camparator which compares two 4-bit words A, B , each word having four Parallel Inputs (A0 – A3, B0 – B3); A3, B3 being the most significant inputs. Operation is not restricted to binary