74LS74A IC Search Results

74ls74a

Abstract: 751A-02
Contextual Info: SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

Contextual Info: GD54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERD FLIP-FLOPS WITH PRESET AND CLEAR Description This device contains two independent D-type positive edge triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the

Contextual Info: H D 74LS74A . Dual D-type Positive Edge-triggered Flip-Flops with Preset and Clear • P IN ARRANGEMENT ■FU N C T IO N TABLE O utputs Inputs P re s e t C lear Clock D Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H X Qo Qo L Notes) H; high level, L; low level, X; irrelevant

74LS74AN

Contextual Info: S E M IC O N D U C T O R tm hold tim es are not violated. A low logic level on the preset or clear inputs will set o r reset th e outputs regardless of the logic levels o f th e o ther inputs. General Description This device contains tw o independent positive-edge-triggered D flip-flops w ith com plem entary o ut­

74LS74AN

Abstract: 54ls74aj 74ls74a ic
Contextual Info: S E M IC O N D U C T O R tm hold tim es are not violated. A low logic level on the preset or clear inputs will se t o r reset th e outputs regardless of the logic levels o f th e o ther inputs. General Description This device contains tw o independent positive-edge-triggered D flip-flops w ith com plem entary o ut­

7474 pin out diagram

Abstract: TTL 7474 7474 D flip-flop circuit diagram 74LS74A pin out configuration specifications 7474 7474 pin configuration 7474 7474 ttl Flip-Flops 7474 pin diagram of 7474
Contextual Info: 7474, LS74A, S74 Signetics Flip-Flops Dual D-Type Flip-Flop Product Specification Logic Products DESCRIPTION The '74 is a dual positive edge-triggered D-type flip-flop featuring individual Data, Clock, Set and Reset inputs; also com­ plementary Q and 5 outputs.

Contextual Info: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR REVISED DECEMBER 1983 Package Options Include Both Plastic and Ceram ic Chip Carriers in Addition to Plastic

74s74

Abstract: 54S74
Contextual Info: SN5474, SN54LS74A, SM54S74, SN7474, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1983 - REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

LS74A

Abstract: e142d SN54L74 SN54H74 SN5474 SN54LS74A SN54S74 SN74 SN74H74 SN74LS74A
Contextual Info: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLiÏ - f Lo P S W % P ^ E T AND C ^A R — _ _ . . . R E V IS E D D E C E M B E R 1 9 83 P ackage O ptions Include Both Plástic and C eram ic Chip Carriers in A dd itio n to Plastic

M74LS74AP

Abstract: 20-PIN
Contextual Info: M IT S U B IS H I LSTTLs M 7 4 L S 7 4 A P DUAL D -TY PE P O SIT IV E ED G E-TR IG G ER ED F LIP -FL O P S W ITH S E T AND R E S E T DESCRIPTION The M 7 4L S 74 A P is a semiconductor intergrated circuit PIN CONFIGURATION TOP VIEW containing 2 D-type positive edge-triggered flip -flo p circuits

74191, 74192, 74193 circuit diagram

Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
Contextual Info: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and

Altera lpm lib 8count

Abstract: 74LS74A EPF8452ALC84 FLEX8000 sram book 8count
Contextual Info: Introduction Viewlogic Powerview design tools and the Altera MAX+PLUS II development software together provide a complete and integrated programmable logic design environment for the Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstation platforms. This

74ls74a ic

Abstract: SN54L74
Contextual Info: TYPES SN5474, SN54H74, SN54L74, SN54LS74A, SN54S74, SN7474, SN74H74, SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR R E V IS E D D E C E M B E R 1983 Package Options Include Both Plástic and Ceram ic Chip Carriers in Addition to Plastic

M5L8284AP

Abstract: M5L8284 5L8284AP M74LS74AP 74ls74ap
Contextual Info: MITSUBISHI LSIs M 5L8284AP CLOCK GENERATOR AND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW Th e M5L8284AP is a clock g e n e ra to r and driver for use with the M E L P S 86, 88 processors. It has a synchronous d e la y circuit and synchronous con­ trol

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

CI 74LS08

Abstract: Altera lpm 8count CI 74LS32 8mcomp 74LS32 Altera lpm lib 8count CI 74LS86 maxplus2 pm lib 8count 74LS161 74LS86
Contextual Info: MENTOR GRAPHICS SOFTWARE ® & MAX+PLUS INTERFACE GUIDE ® II Introduction Mentor Graphics design tools and the Altera MAX+PLUS II development software together provide a complete and integrated programmable logic design environment for the Sun SPARCstation and HP 9000 Series 700

SN74574

Abstract: SN7457 sn7474 SN5474 SN54LS74A SN54S74 SN74 SN74LS74A SN74S74
Contextual Info: SN5474, SN54LS74A, SN54S74, SN7474, SN74LS74A, SN74S74 SDLS119 DUAL 0-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1 9 B 3 - Package Options Include Plastic "Small Outline" Packages. Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

C350AVB

Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
Contextual Info: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices

Truth Table 7485 2 bit comparator

Abstract: IC 7400 pin diagram Truth Table 7485 ic D flip flop 7474 pin DIAGRAM OF IC 7474 74152 data sheet Multiplexer 74152 pin diagram of ic 74ls00 pin diagram for IC 7485 IC TTL 7400 propagation delay
Contextual Info: TM ACTIVE-CAD Real-Time Interactive CAE Tools Logic Simulator User’s Guide Seventh Edition Revision 2 Automated Logic Design Company, Inc. 3525 Old Conejo Rd. #111 Newbury Park, CA 91320 Phone 805 499-6867 Fax (805) 498-7945 Seventh Edition Revision 2, January 15, 1996

bd7995

Abstract: P8243 178M15 transistor b492 TRANSISTOR BJ 131-6 P8035 sk 7443 1334 diode LM1456 LM 8361
Contextual Info: H F To X 8366IT U N E B Issue 2/8534 STR910A B26000 2000 General Wiring Diagram Figure 10.1 +28 V sense) GROUND Meter Batt. sense + Sense Isolated Ground Batt. GND O FF 28 V O FF (T X O F F ) Relays K4, K1 & K2 BATT. MODE »DC» Relays K5, K6 +8 V in GROUND

PT3983

Abstract: Valor Electronics pt3983 coupling transformer ethernet tp-link fl1020 FL1010 palce programming algorithm power generation POWER COMMAND Hmi 211 fp 101g palce16v8 programming algorithm isa-hub
Contextual Info: IEEE 802.3 Repeater Technical Manual A D V A N C E D M I C R O D E V I C E S  1993 Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics.

IEEE Standard 1014-1987

Abstract: GPIB-1014 diack 5b HD68450 MC68450 PD7210 LS2521 GTM 5010 25ls2521 scr205
Contextual Info: GPIB-1014 User Manual March 1997 Edition Part Number 320030-01 Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved. National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 512 794-0100 Technical support phone: (512) 795-8248

IEEE Standard 1014-1987

Abstract: NEC uPD7210 F1241 LS2521 GPIB-1014 HD68450 MC68450 PD7210 GTM 5010
Contextual Info: GPIB-1014 User Manual March 1997 Edition Part Number 370945A-01 Copyright 1985, 1997 National Instruments Corporation. All Rights Reserved. National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 512 794-0100 Technical support phone: (512) 795-8248