74LS273 IC Search Results

74LS273

Abstract: pin diagram of 74ls273 1619CP SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS273 OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3

74LS273

Abstract: pin diagram of 74ls273 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXN
Contextual Info: SN54/74LS273 OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3

74LS273

Abstract: DTLLA 74S273 74LS N74LS273D N74LS273N N74S273D N74S273N 74LS273 equivalent FM04
Contextual Info: Signetics 74LS273, S273 Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

74LS273

Contextual Info: Sjgnetìcs 74LS273, S273 Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES TYPE • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

74LS273

Contextual Info: Am25LS273 • Am25LS273B Am54LS/74LS273 8-Bit Register with Clear 8-Bit Register with Clear and Buffered Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • Eight-bit, high-speed parallel registers • Clock to output delay - 15ns typ on Am25LS273

ls273

Abstract: 74LS273 AM25LS273PC 74LS AM25LS273DC AM25LS273DM AM25LS273FM AM25LS273XC AM25LS273XM SN74LS273N
Contextual Info: Am25LS273 • Am25LS273B Am54LS/74LS273 8-Bit Register with Clear 8-Bit Register with Clear and Buffered Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • Eight-bit, high-speed parallel registers • C lock to output delay - 15ns typ on Am25LS273

IC 74LS273

Abstract: 74ls273 IC 74LS273 P pin diagram of 74ls273
Contextual Info: 74LS273, S273 Signetìcs Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

Contextual Info: GD54/74LS273 OCTAL D-TYPE FLIP-FLOPS COMMON CLOCK SINGLE-RAIL OUTPUTS Feature • • • • Pin Configuration Contains Eight Flip-Flops with Single-Rail Outputs Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications Include:

Contextual Info: GD54/74LS273 OCTAL D-TYPE FLIP-FLOPS COMMON CLOCK SINGLE-RAIL OUTPUTS Feature • Pin Configuration Contains Eight Flip-Flops with Single-Rail Outputs • Buffered C lo ck and D irect C lear Inputs • Individual Data Input to Each Flip-Flop V çc • Applications Include:

IC 74LS273 P

Abstract: 74LS273 74ls273 IC 74LS 74S273 N74LS273D N74LS273N N74S273D N74S273N pin diagram of 74ls273
Contextual Info: Signetìcs 74LS273, S273 Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available TY PE T Y PICA L T Y PICA L S U P P LY C U R R E N T

74LS273

Abstract: IC 74LS273
Contextual Info: PANASONIC INDL/ELEK { I O 75 ]>e . bl35flS5 0007500 & 6 9 3 2 8 5 2 PANASONIC I N O L*ELECTR O N IC 72C 0 7 2 00 LS TTL DN74LS5>U—X &&*;• DN74LS273/DN74LS273S DN74LS273 DN74LS273S Octal D-type Flip-F lops (with Reset D N 74LS273/S l i , .& |5 ]& £ }g Wü;*g ' i - t y

74LS273

Abstract: pin diagram of 74ls273 74LS273 equivalent 54LS 74LS
Contextual Info: GD54/74LS273 OCTAL D-TYPE FLIP-FLOPS COMMON CLOCK SINGLE-RAIL OUTPUTS F eature • • • • Pin C o n fig u ra tio n Contains Eight Flip-Flops with Single-Rail O utputs B uffered C lock and D irect Clear Inputs Individual Data Input to Each Flip-Flop A pplications Include:

Contextual Info: 273 CO NNECTIO N DIAGRAM PINOUT A 54LS/74LS273 // s ^V 8-BIT REGISTER With Clear DESCRIPTION — The ’273 is a high speed 8-bit register, consisting of eight D-type flip -flo p s w ith a com m on C lock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch

74198

Abstract: 74LS194 74198 pin diagram 54LS D172 D173 74LS273 74LS323 74ls273 fairchild 74LS398
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL 088 54LS/74LS299 11 18 Vcc Pin 20 QND = Pin 10 D89 54LS/74LS323 Vcc = Pin 20 QND = Pin 10 D90 54LS/74LS273 3 4 7 8 13 14 17 18 Vcc = Pin 20 GND = Pin 10 D91 54LS/74LS377 1 3 4 7 8 13 14 17 18 Vcc = Pin 20 GND = Pin 10

74LS273

Contextual Info: M M O T O R O L A SN54/74LS273 D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 2 7 3 is a h ig h -sp eed 8-B it Register. The register co nsists of eight D-Type Flip-Flops w ith a Com m on Clock and an asynchronou s active L O W M aster Reset. This device is sup p lied in a 20-pin package featuring 0 .3 inch lead spacing.

74LS74

Abstract: 74LS244 81 74ls24 LS273 74LS138 74LS244 74LS273 74LS322 u3 74ls138 EPROM27512
Contextual Info: h 4 3 5 0 0 2 f t fit M fc n .| ~ rf S i W . i i i i t A i t • i t inclu de < c o o i o , hp> i t inclu de < s t r in g . H > A K {iW .i# iiT < it« lW a fim .3 R F E ft5 i# i» 5 !I# > T « l # , * T E m w s t i i E f c * 0 Jit J t m t m f m a # inclu de < c t y p e . h >

74LS273

Abstract: MM74HC273N 74HC273
Contextual Info: Revised February 1999 MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits.

IC 74273

Abstract: 74273 IC 74LS273 TTL 74273
Contextual Info: SN54273, SN 54LS273, SN 74 2 73 . SN 74LS 2 73 O C TAL D T Y P E FLIP FLO P WITH CLEAR OCTOBER 1 9 7 6 - REVISED M AR C H 1 9 8 8 S N 5 4 2 7 3 , S N 7 4 L S 2 7 3 . . . J OR W PACKAG E Contains Eight Flip-Flops with Single-Rail Outputs S N 74273. . N PACKAGE

Contextual Info: SbE T> m ISGTH 7^2*123? 004D1QQ 04G T - ^ 6 -0 7 - I / M54HC273 M74HC273 SCS-THOMSON 0 © [l[L i© ir K S R il0 © S G S-THOMSON OCTAL D-TYPE FLIP FLOP WITH CLEAR • HIGH SPEED fMAX = 48 MH z (TYP.) at VCc = 5V ■ LOW POWER DISSIPATION ICC = 4 M (MAX.) at TA = 25°C

M74HCT273

Contextual Info: r r z SGS-THOMSON Ä 7# M54HCT273 M74HCT273 OCTAL D TYPE FLIP FLOP WITH CLEAR • HIGH SPEED f MAX = 80 MHz TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 \iA (MAX.) AT T a = 25 'C ■ CO M PATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX)

TC40H273P

Abstract: S 178 A INTEGRATED CIRCUIT IC 74LS273
Contextual Info: TO SHIBA INTEGRATED CIRCUIT TECHNICAL DATA T P d . n M I U “ TC40H273 9 7 ' l P / F I U l / I C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC U l l f c OCTAL D-TYPE FLIP-FLOP The TC40H273 is octal D-type flip-flop having common CLOCK terminal and CLEAR terminal.

Contextual Info: M54HC273 M74HC273 SGS-THOMSON IU OCTAL D TYPE FLIP FLOP WITH CLEAR • HIGHSPEED fMAX = 67 MHz TYP. AT VCc = 5 V ■ LOW POWER DISSIPATION Ice = 4 nA (MAX.) AT T a = 25 ”C . HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

Contextual Info: I SGS-THOMSON M54HC273 AT fw[M0«m [iC T » S_ M74HC273 OCTAL D-TYPE FLIP FLOP WITH CLEAR • HIGH SPEED fMAX = 48 MHz (TYP. at VCC= 5V ■ LOW POWER DISSIPATION lCC = 4 /iA (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY V n !H = VniL= 280/o V CC (MIN).

Contextual Info: SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D TYPE FLIP-FLOP WITH CLEAR OCTOBER 1976 - REVISED MARCH 1988 S N 5 4 2 7 3 , S N 7 4 L S 2 7 3 . . . J OR W P A C K A G E Contains Eight Flip-Flops with Single-Rail Outputs SN 74273 . . . N PACKAG E S N 7 4 L S 2 7 3 . . . DW OR N P A C K A G E