74HCT1 Search Results
74HCT1 Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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CD74HCT10M96 |
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High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 |
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CD74HCT109E |
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High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
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CD74HCT132M96 |
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High Speed CMOS Logic Quad Schmitt-Triggered 2-Input NAND Gates 14-SOIC -55 to 125 |
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CD74HCT137M96 |
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High Speed CMOS Logic 3-to-8 Line Decoder/Demultiplexer with Address Latches 16-SOIC -55 to 125 |
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CD74HCT139M96 |
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High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
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74HCT1 Datasheets (500)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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74HCT1 |
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10-to-4 line priority encoder | Original | 45.41KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT10 |
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Triple 3-Input NAND Gate | Original | 30.49KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107 |
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Dual JK flip-flop with reset negative-edge trigger | Original | 50.01KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D |
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Dual JK flip-flop with reset negative-edge trigger | Original | 55.15KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 33.05KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D,652 |
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Bulk Pack, CECC | Original | 49.98KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D,653 |
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT108-1 (SO14); Container: Reel Pack, SMD, 13", CECC | Original | 49.98KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107DB |
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Dual JK Flip-Flop with Reset, Negative-Edge Trigger | Original | 50KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D-Q100 |
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Dual JK flip-flop with reset; negative-edge trigger | Original | 138.63KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D-Q100J |
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74HCT107D-Q100 - 74HCT107D-Q100 - Dual JK flip-flop with reset; negative-edge trigger | Original | 138.61KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D-T |
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Dual JK flip-flop with reset negative-edge trigger | Original | 50.01KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107D-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 33.05KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107DW |
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Dual JK flip-flop with reset, negative-edge trigger | Original | 55.15KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107N |
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Dual JK flip-flop with reset negative-edge trigger | Original | 55.15KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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74HCT107N | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 33.05KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107N,652 |
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Dual JK flip-flop with reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 73 MHz; Logic switching levels: TTL ; Number of pins: 14 ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 16 ns; Voltage: 4.5-5.5V; Package: SOT27-1 (DIP14); Container: Bulk Pack, CECC | Original | 49.98KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107PW |
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Dual JK Flip-Flop with Reset, Negative-Edge Trigger | Original | 50KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT107U |
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Dual JK flip-flop with reset negative-edge trigger | Original | 55.15KB | 7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT109 |
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Dual J invertedK flip-flop with set and reset positive-edge trigger | Original | 57.64KB | 9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74HCT109D |
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Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger | Original | 57.63KB | 9 |
74HCT1 Price and Stock
Texas Instruments CD74HCT126M96IC BUFF NON-INVERT 5.5V 14-SOIC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HCT126M96 | Digi-Reel | 7,313 | 1 |
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CD74HCT126M96 | 2,348 |
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CD74HCT126M96 | 51,000 | 1 |
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CD74HCT126M96 | 2,237 |
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CD74HCT126M96 | 600 |
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Texas Instruments CD74HCT161M96IC BINARY COUNTER 4-BIT 16SOIC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HCT161M96 | Cut Tape | 6,885 | 1 |
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CD74HCT161M96 | 690 | 12 |
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Texas Instruments CD74HCT14M96IC INVERT SCHMITT 6CH 1IN 14SOIC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HCT14M96 | Digi-Reel | 3,218 | 1 |
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CD74HCT14M96 | 3,187 |
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CD74HCT14M96 | 2 | 1 |
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CD74HCT14M96 | 1,450 |
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CD74HCT14M96 | Cut Tape | 1,770 | 0 Weeks, 1 Days | 5 |
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CD74HCT14M96 | 15,370 |
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CD74HCT14M96 | 126 |
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CD74HCT14M96 | 11,870 |
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Texas Instruments CD74HCT163MIC BINARY COUNTER 4-BIT 16SOIC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HCT163M | Tube | 1,122 | 1 |
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CD74HCT163M | 26,715 | 1 |
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Texas Instruments CD74HCT107EIC FF JK TYPE DBL 1-BIT 14-PDIP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HCT107E | Tube | 1,077 | 1 |
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CD74HCT107E | 425 | 4 |
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CD74HCT107E | 21,945 | 1 |
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74HCT1 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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IC 74HC112
Abstract: 74HC112
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CD54/74HC112, CD54/74HCT112 SCHS141A HC112 HCT112 loSZZU001B, SDYU001N, SCET004, SCAU001A, CD74HC112E IC 74HC112 74HC112 | |
74HC109Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features |
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CD54/74HC109, CD54/74HCT109 SCHS140A HC109 HCT109 SCLA008 SZZU001B, SDYU001N, SCET004, SCAU001A, 74HC109 | |
CD74HC138MT
Abstract: CD74HC138M96E4 74HC138
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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 SCHS147I CD54HC138F3A CD54HC238F3A CD54HCT138F3A CD54HCT238F3A CD74HC138E CD74HC138MT CD74HC138M96E4 74HC138 | |
74HC
Abstract: 74HC126 74HC1G126 74HC1G126GV 74HC1G126GW 74HCT126 74HCT1G126 74HCT1G126GV 74HCT1G126GW
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74HC1G126; 74HCT1G126 74HC1G126 74HCT1G126 74HC126 74HCT126. HCT1G126 74HC 74HC1G126GV 74HC1G126GW 74HCT126 74HCT1G126GV 74HCT1G126GW | |
21A1
Abstract: 74LV125DB 74HC125 74HCT125 74LV125 74LV125D 74LV125N 74LV125PW JESD22-A114E
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74LV125 74LV125 74HC125 74HCT125. 21A1 74LV125DB 74HCT125 74LV125D 74LV125N 74LV125PW JESD22-A114E | |
74HC123
Abstract: 74HCT123 74LV123 74LV123BQ 74LV123D 74LV123DB 74LV123N 74LV123PW SOT736-1
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74LV123 74LV123 74HC123; 74HCT123. 74HC123 74HCT123 74LV123BQ 74LV123D 74LV123DB 74LV123N 74LV123PW SOT736-1 | |
CD54HC158
Abstract: CD74HC158 HC157 HC158
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CD74H CT157, CT158) CD54HC158 CD74HC158 CD54/74HC157, CD54/74HCT157, HC157 HC158 | |
Contextual Info: [ /Title CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8 /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/ |
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HC138 HCT13 HC238 HCT23 CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 SCHS147I CD54HC138F3A | |
SCHS142F
Abstract: 74HC123 74HC123 timing application circuits of ic 74HC123 CD54HC123F3A CD54HCT123F3A CD74HC123E CD74HC123M CD74HC123M96 CD74HC123MT
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HC123 HCT12 HC423 HCT42 CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 SCHS142F CD54HC123F3A SCHS142F 74HC123 74HC123 timing application circuits of ic 74HC123 CD54HC123F3A CD54HCT123F3A CD74HC123E CD74HC123M CD74HC123M96 CD74HC123MT | |
HC192Contextual Info: [ /Title CD74 HC192 , CD74 HC193 , CD74 HCT19 3 /Subject (High Speed CMOS Logic Preset- CD54/74HC192, CD54/74HC193, CD54/74HCT193 Data sheet acquired from Harris Semiconductor SCHS163D September 1997 - Revised December 2002 High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters |
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 SCHS163D HC192, HC193 HCT193 5962-9084801MEA 9084801MEAS2035 CD54HCT193F3A HC192 | |
CD74HCT138/238Contextual Info: Technical Data File N um b er CD54/74HC138, CD54/74HCT138 CD54/74HC238, CD54/74HCT238 1477 HARRIS SEMICOND SECTOR 57E D B 4302E71 DQlTSTh 0 « H A S High-Speed CMOS Logic H C /H C T H C /H C T 238 138 m -v o d f i i ; 12 Y3 - l i — Y4 - y - v s Y6 — — Y7 |
OCR Scan |
CD54/74HC138, CD54/74HCT138 CD54/74HC238, CD54/74HCT238 4302E71 54/74H CD54/74HCT138 54/74HC 54/74HC S4/74HC CD74HCT138/238 | |
74HC123
Abstract: 74HC123D 74hc123 application note 74hc123 application notes 74HCT123D 74HCT123N 74HCT423 74HC123N 74HC423 74HCT123
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74HC123; 74HCT123 74HCT123 HCT123 74HC123 74HC123D 74hc123 application note 74hc123 application notes 74HCT123D 74HCT123N 74HCT423 74HC123N 74HC423 | |
Contextual Info: [ /Title CD74 HC139 , CD74 HCT13 9 /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod CD54/74HC139, CD54/74HCT139 Data sheet acquired from Harris Semiconductor SCHS148B High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer September 1997 - Revised May 2000 |
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CD54/74HC139, CD54/74HCT139 SCHS148B CD4556B 8409201EA CD54HC139F CD54HC139F3A 8409201EA | |
74HC163
Abstract: hc163 cd74hc161 hct163
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CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 SCHS154A HC161 HCT161 8607601EA CD54HC163F3A 8607601EA 74HC163 hc163 cd74hc161 hct163 | |
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Contextual Info: GD54/74HC165, GD54/74HCT165 8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER General Description Pin Configuration These devices are identical in pinout to the 5 4 /74L S 16 5 . This circuit is an 8-bit, parallel-input to serial-output shift register with complementary |
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GD54/74HC165, GD54/74HCT165 | |
HCT163A
Abstract: 74HCT161 LS161A LS163A MC54HCXXXAJ MC74HCXXXAD MC74HCXXXAN
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MC54/74HCT161A MC54/74HCT163A MC54/74HCT161A HCT163A LS161A LS163A. HCT161A MC54/74HCT161A/D* MC54/74HCT161A/D 74HCT161 LS161A LS163A MC54HCXXXAJ MC74HCXXXAD MC74HCXXXAN | |
74HC164N PIN DIAGRAM
Abstract: 74hc164n 74HCT164 application note 74HC164 74HCT164 74HCT164BQ 74HC164D 74HC164DB 74HCT164D 74HCT164DB
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74HC164; 74HCT164 74HCT164 HCT164 74HC164N PIN DIAGRAM 74hc164n 74HCT164 application note 74HC164 74HCT164BQ 74HC164D 74HC164DB 74HCT164D 74HCT164DB | |
74HC163
Abstract: CP/2014
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74HC163; 74HCT163 74HCT163 HCT163 74HC163 CP/2014 | |
74HC163
Abstract: CP/2014
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74HC163-Q100; 74HCT163-Q100 74HCT163-Q100 HCT163 74HC163 CP/2014 | |
Contextual Info: 74HC175; 74HCT175 Quad D-type flip-flop with reset; positive-edge trigger Rev. 3 — 31 March 2014 Product data sheet 1. General description The 74HC175; 74HCT175 are high-speed Si-gate CMOS devices which are pin compatible with Low-power Schottky TTL LSTTL . |
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74HC175; 74HCT175 74HCT175 HCT175 | |
PC 74HC139Contextual Info: [ /Title CD74 HC139 , CD74 HCT13 9 /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod CD54/74HC139, CD54/74HCT139 Data sheet acquired from Harris Semiconductor SCHS148B High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer September 1997 - Revised May 2000 |
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HC139 HCT13 CD54/74HC139, CD54/74HCT139 SCHS148B CD4556B PC 74HC139 | |
74hc153Contextual Info: [ /Title CD74H C153, CD74H CT153 /Subject (High Speed CMOS Logic Dual 4Input CD54/74HC153, CD54/74HCT153 Data sheet acquired from Harris Semiconductor SCHS151A High Speed CMOS Logic Dual 4-Input Multiplexer September 1997 - Revised May 2000 Features Description |
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CD74H CT153) CD54/74HC153, CD54/74HCT153 SCHS151A HC153 HCT153 74hc153 | |
74HC165
Abstract: HC165 74HC165 logic diagram
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CD74H CT165) CD54/74HC165, CD54/74HCT165 SCHS156A HC165 HCT165 74HC165 74HC165 logic diagram | |
ic 74HC164 AND SPECIFICATIONS
Abstract: ic cmos 74hc164 CD74HC164M 74HCT164 74HC164 HC164 CD54HC164F 74HCT164 diagram
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HC164 HCT16 CD54/74HC164, CD54/74HCT164 SCHS155A HC164 HCT164 ic 74HC164 AND SPECIFICATIONS ic cmos 74hc164 CD74HC164M 74HCT164 74HC164 CD54HC164F 74HCT164 diagram |