74LS390 Search Results

74LSOO

Abstract: HD74LS390 Hitachi Scans-001
Contextual Info: • Dual Decade Counters I BLOCK DIAGRAM {'A This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement two individual four-bit counters. The H D 74LS390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement cycle

74LS390

Abstract: 74LS393 equivalent 74LS393 LS290 LS293 LS390 LS393
Contextual Info: SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input

ttl 74LS173

Abstract: ttl 7497 74ls390 D187 D188 D190 D194 D195 D196
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 14 15 k h 12 1 1 — 0 CE TC CP ;=3ID OE Gy D194 54LS/74LS390 each half) 15 1 ,1 5 - CPo 4 ,1 2 - CPi M R Oo Q i Qz 03 2 ,1 4 5,11 3, 13 V c c = Pin 16

Contextual Info: GD54/74LS390 DUAL 4-BIT DECADE AND BINARY COUNTERS Features Pin Configuration • Dual Versions of the Popular ‘LS90 • ‘LS390. Individual Clocks for A and B Flip-Flops Provide Dual-r 2-^5andCounters • Direct Clear for Each 4-Bit Counter • Dual 4-Bit Version Can Significantly Improve

Contextual Info: 74LS390 Signetics Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

N74LS390N

Abstract: 1N3064 1N916 74LS 74LS390 N74LS390D decade counter circuit diagram CP012
Contextual Info: Signetics 74LS390 Counter Dual Decade R ipple C ounter Product Specification L o g ic P roducts FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 o r 100 • Two Master Resets to clear each

74LS390

Abstract: binary to BCD 8421 74LS393 equivalent SN54-74LS390 74LS393 LS390 LS290 LS293 LS393
Contextual Info: SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input

74LS393

Abstract: LS390
Contextual Info: M M O T O R O L A . DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54/74LS390 and SN54/74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input

Contextual Info: SN54390, SN54LS390, SN54393, SN54LS393, SN74390, 74LS390, SN74393, SN74LS393 DUAL 4 BIT DECADE AND BINARY COUNTERS OCTOBER 1976 - S N 7 4 3 9 0 . . . N P AC K A G E SN 74LS390 . D OR N P AC KA G E '390, 'LS390 . . . Individual Clocks for A and B Flip-Flops Provide Dual + 2 and 5 Counters

74HCT390

Contextual Info: GD54/74HC390, GD54/74HCT390 DUAL 4-BIT DECADE COUNTERS General Description These devices are identical in pinout to the 54/74LS390. They incorporate two independent 4-Bit decade counters, each composed of a divideby-2 and a divide-by-5 counter. The divide-by-2 and

D flip-flop 74175 pin

Abstract: 74175 D flip flop D134 8-bit ttl latch 93L38 74LS573 ttl 7497 D187 D188 D190
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 14 15 k h 12 Ü 13 IE 11 — 0 CE 9 - CP 10— 0 Ez 1 2 - Gy TC OE D190 54LS/74LS375 D194 54LS/74LS390 each half) 15 1 ,1 5 - CPo 4 ,1 2 -

74LS390

Abstract: 1N3064 74LS N74LS390D N74LS390N decade counter circuit diagram
Contextual Info: 74LS390 Signetics Counter Dual D ecade Ripple C o un ter Product Specification Logic Products FEA TURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two Master Resets to clear each

74LS39

Abstract: 74LS393 74LS390 LS390 751A-02 LS290 LS293 LS393 SN54LSXXXJ SN74LSXXXN
Contextual Info: <g> MOTOROLA. SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54/74LS390 and SN54/74LS393 each contain a pair < high-speed 4-stage ripple counters. Each half of the LS390 is parti: ned into a divide-by-two section and a divide-by five section, with a sepan- i clock input

dual 4 bits decade counter

Abstract: 74LS390
Contextual Info: 74LS390 Signetics Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, S, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

74LS390

Contextual Info: Signetics 74LS390 Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

74LS390N

Contextual Info: 74LS390 Signetics Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 TY P E 74LS390 P A C K A G ES DESCRIPTION

Contextual Info: TOSHIBA TC74HC390AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC390AP, TC74HC390AF, TC74HC390AFN Note The JEDEC SOP (FN) is not available in Japan DUAL DECADE COUNTER The TC74HC390A is a high speed CMOS DUAL DECADE COUNTER fabricated with silicon gate C2MOS technology.

TC74HC390A

Contextual Info: TOSHIBA TC74HC390AP/AF/AFN Dual Decade Counter The TC74HC390A is a high speed C M O S DUAL DECADE COUNTER LATCH fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the C M O S low power dissipation.

74HC390

Abstract: M54HC390 M54HC390F1R M74HC390 M74HC390B1R M74HC390C1R M74HC390M1R
Contextual Info: M54HC390 M74HC390 DUAL DECADE COUNTER . . . . . . . . HIGH SPEED fMAX = 84 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

M74HC390

Abstract: M54HC390 M54HC390F1R M74HC390B1R M74HC390C1R M74HC390M1R
Contextual Info: M54HC390 M74HC390 DUAL DECADE COUNTER . . . . . . . . HIGH SPEED fMAX = 84 MHz TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

74HC

Abstract: 74LS390 74LS393 C1995 MM74HCA390 MM74HCA393 smb schottky diode s4
Contextual Info: MM74HCA390 Dual 4-Bit Decade Counter MM74HCA393 Dual 4-Bit Binary Counter General Description These counter circuits contain independent ripple carry counters and utilize advanced silicon-gate CMOS technology The MM74HCA390 incorporates dual decade counters

ttl 7497

Abstract: 74167 D196 D187 D188 D190 D194 D195 74167 logic diagram
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 11 — 0 CE 14 15 k h Ü 13 12 IE 7 9 - CP 10—0 Ez 1 2 - Gy TC ;=3ID 1 ,1 5 - CPo 4 ,1 2 - C Pi MR Oo Q i Qz 03 2,14 5,11 7,9 3, 13 8, 10

74LS390N

Abstract: 31165 74HC08N 74AC11074N ADS7812 ADS7813 ADS7813PB IRF7604 OPA627BP HD411-2
Contextual Info: DEM-ADS7812/13P EVALUATION FIXTURE FEATURES DESCRIPTION ● COMPUTER INTERFACE The DEM-ADS7812/13P evaluation fixture is designed for quick evaluation of Burr-Brown’s ADS7812 and ADS7813. Breadboard areas are provided with optional bipolar power supply connections to assist in