74ACT273 Search Results

Contextual Info: 74AC273, 74ACT273 Octal D-Type Flip-Flop Features General Description • Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master

74ACT273

Abstract: 74ACT273TTR 74ACT273B 74ACT273M 74ACT273MTR DIP-20
Contextual Info: 74ACT273 OCTAL D-TYPE FLIP FLOP WITH CLEAR • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190MHz TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING

ACT273

Abstract: 74ACT273 74ACT273B 74ACT273M DIP-20
Contextual Info: 74ACT273  OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190 MHz ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX)

sc1097

Abstract: sc10970 SC10980 sc1098 SC-1097 74ACT273 74ACT273B 74ACT273M ACT273 DIP-20
Contextual Info: SGS-THOMSON 74ACT273 M IM i[Li gïïlHΩiD(3S OCTAL D-TYPE FLIP FLOP W ITH CLEAR PRELIM IN ARY DATA . . . . . . HIGHSPEED: fMAX = 190 MHz ns (TYP.) at Vcc = 5V LOW POWER DISSIPATION: Icc = 8 |xA (MAX.) at T a = 25 °C COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V (MAX)

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: Revised March 2005 74AC273 • 74ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

ACT273

Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/74ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops

MC74AC273

Abstract: MC74AC373
Contextual Info: MC74AC273, 74ACT273 Octal D Flip−Flop The MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously.

MC74AC273

Abstract: MC74AC373 ACT273 MC74AC374 MC74AC377 MC74ACT273
Contextual Info: MC74AC273, 74ACT273 Octal D Flip−Flop The MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously.

SC1098

Abstract: 74ACT273
Contextual Info: 74ACT273 OCTAL D-TYPE FLIP FLOP WITH CLEAR PR ELIM IN ARY DATA . HIGHSPEED: fMAX = 190 MHz ns TYP. at Vcc = 5V . LOW POWER DISSIPATION: Ice = 8 jiA (MAX.) at Ta = 25 °C . COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V(MAX) • 50£2 TRANSMISSION LINE DRIVING

MC74ac273

Abstract: ACT273 MC*ac273 MC74AC373
Contextual Info: MC74AC273, 74ACT273 Octal D Flip-Flop The MC74AC273/74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously.

74ACT273

Abstract: act273 74ACT273B 74ACT273M 74ACT273T DIP-20
Contextual Info: 74ACT273  OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 190 MHz ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX)

MC74AC273

Abstract: MC74AC373 ACT273 MC74AC273DW MC74AC273N MC74AC374 MC74AC377 MC74ACT273 MC74ACT273N 74AC273
Contextual Info: MC74AC273, 74ACT273 Octal D Flip-Flop The MC74AC273/74ACT273 has eight edge-triggered D–type flip–flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip–flops simultaneously.

cd74ac273

Abstract: 74ACT273
Contextual Info: Technical Data _ CD54/74AC273 CD54/74ACT273 Octal D Flip-Flop with Reset Type Feature»: • B uffered inputs a Typical propagation delay: 6.5 ns @ Vcc - 5 V, 7V = 25° C, CL = 50 pF The RCA CD54/74AC273 and CD54/74ACT273 are octal D flip -flo p s w ith reset that use the RCA ADVANCED CMOS

74AC273

Abstract: 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273SC 74ACT273SJ AC273 ACT273
Contextual Info: 74AC273, 74ACT273 Octal D-Type Flip-Flop Features General Description • Ideal buffer for microprocessor or memory The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master

74ACT273SC

Abstract: AC273 74AC273 74AC273MTC 74AC273PC 74AC273SC 74AC273SJ 74ACT273 74ACT273MTC ACT273
Contextual Info: Revised October 1999 74AC273 • 74ACT273 Octal D-Type Flip-Flop General Description Features The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) input

74ACT273

Contextual Info: S G S -T H O M S O N [MSIfiiSilLiSìlKìtÉfflOSS 74ACT273 OCTAL D-TYPE FLIP FLOP WITH CLEAR PRELIM IN ARY DATA . HIGHSPEED: fMAX = 190 MHz ns TYP. at Vcc = 5V . LOW POWER DISSIPATION: Icc = 8 |xA (MAX.) at Ta = 25 °C . COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), Vil = 0.8V (MAX)

ACT273

Abstract: ac273 74AC
Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/74ACT273 O ctal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has e ig h t edge-triggered D-type flip -flo p s w ith individual D in p u ts and Q outputs. The com m on buffered C lock CP and M aster Reset

MC74ac273

Abstract: MC74AC373
Contextual Info: MC74AC273, 74ACT273 Octal D Flip-Flop The MC74AC273/74ACT273 has eight edge-triggered D–type flip–flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip–flops simultaneously.

Contextual Info: Technical Data _ CD54/74AC273 CD54/74ACT273 Octal D Flip-Flop with Reset Type Features: • Buffered inputs m Typical propagation delay: 6.5 n s @ V cc = 5 V, I * = 25° C, CL ; 50 pF RESET THU 1 M C S-S6»76R 2 FUNCTIONAL DIAGRAM The RCA CD54/74AC273 and CD54/74ACT273 are octal D

MC74AC273

Abstract: MC74AC373
Contextual Info: Octal D FlipĆFlop The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one

ACT273

Abstract: AC273
Contextual Info: AC273 • ACT273 54AC/74AC273 • 54ACT/74ACT273 Octal D Flip-Flop Description Connection Diagrams The ’AC/’ACT273 has eight edge-triggered D-type flip-flops w ith individual D inputs and Q outputs. The common buffered Clock CP and Master Reset (15ÎÏÏ) inputs load and reset (clear) all flip-flops

ACT273

Abstract: 74AC mr 800 diode CP000
Contextual Info: National Semiconductor 54AC/74AC273 • 54ACT/74ACT273 Octal D Flip-Flop General Description Features The ’A C /’ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buff­ ered Clock CP and Master Reset (MR) input load and re­

74AC273

Abstract: 74AC273MTC 74AC273SC 74AC273SJ 74ACT273 AC273 ACT273 M20D MS-013 MTC20
Contextual Info: A I R C H N ovem ber 1988 I L D Revised O ctober 1999 S E M IC D N D U C T Q R T M 74AC273 • 74ACT273 Octal D-Type Flip-Flop General Description Features The AC 273 and AC T273 have eight edge-triggered D-type flip-flops with individual D -type inputs and Q outp u ts . The

MC74AC273

Abstract: MC74AC373
Contextual Info: M M O T O R O L A M C 7 4A C 27 3 M C 74A C T 273 O c ta l D Flip-Flop OCTAL D FLIP-FLOP The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with indi­ vidual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.