7476 IC Search Results

IC 7476

Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
Contextual Info: FAIRCHILD TTL/SSI . 9N76/5476, 7476 D UA L JK M A STER /SLA VE F LIP -F LO P W ITH SEPARATE PRESETS, CLEARS A N D CLOCKS DESCRIPTION — The T TL/S SI 9N 76 /54 7 6 , 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks.

PIN CONFIGURATION 7476

Abstract: pin diagram of 7476 7476 PIN DIAGRAM 7476 FUNCTION TABLE pin diagram of ttl 7476 7476 pin configuration LS 7476 7476 PIN DIAGRAM input and output 74LS76 J-K Flip-Flop 7476
Contextual Info: 7476, LS76 Sjgnetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the

pin diagram of 7476

Abstract: 7476 FUNCTION TABLE 7476 J-K Flip-Flop PIN CONFIGURATION 7476 7476 PIN DIAGRAM 7476 Jk 74ls76 pin out 74LS76 7476 PIN DIAGRAM input and output J-K Flip-Flop 7476
Contextual Info: 7476, LS76 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with Individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the

jk flip flop 7476

Abstract: 7476 PIN DIAGRAM 7476 7476 ttl 7476 PIN DIAGRAM input and output TTL 74ls76 pin diagram of 7476 PIN CONFIGURATION 7476 7476 J-K Flip-Flop pin diagram of ttl 7476
Contextual Info: Signetics 7476, LS76 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-trig­ gered. JK information is loaded into the

pin diagram of 7476

Abstract: 74LS76 PIN CONFIGURATION 7476 7476 PIN DIAGRAM input and output Jk 74ls76 pin out 7476 FUNCTION TABLE 7476 J-K Flip-Flop 7476 pin configuration TTL 7476 7476 logic diagram
Contextual Info: 7476, LS76 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '76 is a dual J-K flip-flop with individual J, K, Clock, Set and Reset inputs. The 7476 is positive pulse-triggered. JK information is loaded into the master while the Clock is HIGH and

7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram of 7476 S5476F PIN CONFIGURATION 7476 7476 7476 pin configuration
Contextual Info: 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76” is a D ual J K F lip -F lo p w ith in d iv id ­ ual J, K, C lock, S et and Reset inpu ts. Th e 7476 and 74H76 are p o sitive pulse trig g e re d flip -flo p s . JK in fo rm a tio n is loaded in to the m aster w h ile the C lock is H IG H and tra n s ­

CI 7473

Abstract: counter with 7473 7490 Decade Counter 7476 up down counter 7476 counter ci 74192 decade counter 7492 74122 Retriggerable Monostable Multivibrator ci 7476 7490 counter
Contextual Info: BIPOLAR DIGITAL ICs continued :lip-flops T 7472/5472 T 7473/5473 T 7474/5474 T 7476/5476 T 74107/54107 T 74121/54121 T 74122/54122 T 74123/54123 Jther functions T 7441 A/5441 A T 7442/5442 T 7443/5443 T 7444/5444 T 7475/5475 T 7481/5481 T 7483/5483 T 7484/5484

logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 logic ic 7476 flip-flop pin diagram 7476 truth table pin diagram for IC 7476 pin configuration of 74LS76 IC IC 74LS76 logic ic 74LS76 pin diagram 74Ls76 truth table 74LS80
Contextual Info: 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION ORDERING CODE PACKAGES PIN CONF. 2 The 74LS76 is a negative edge triggered flip-flop. The J and K inputs must be stable only one setup time prior to the HIGH-toLOW Clock transition. The Set Sd and Reset (Rd ) are asynchro­

74ls76 jk flip-flop logic symbol and truth table

Abstract: 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop pin diagram of 7476 74LS76D 74LS76DC Jk 74ls76 pin out
Contextual Info: 76 CONNECTIO N DIAGRAM PINOUT A ^54/7476 OZZô/b> ^54H /74H 76 G f / c t l l/54LS/74LS76 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks c p i [T DESCRIPTION — The ’76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip -flop .

7476 truth table

Abstract: 7476 logic diagram 74LS76P 7476PC 74ls76
Contextual Info: NATIONA L SEMICOND -CLOGIO 02E D | b S O U S E 76 GGbBVSO t, | 3 T-ŸL- 0 7 -0 7 CONNECTION DIAGRAM PINOUT A 54/7476 54H/74H76 54LS/74LS76 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks DESCRIPTION — The '76 and 'H76 are dual JK master/slave flip-flops with

74LS76P

Abstract: 74LS76D IC 7476 pinout logic ic 7476 flip-flop pin diagram and pin diagram of IC 7476 logic ic 7476 pin diagram 7476PC 74H76 74LS76 pinout 74LS76 IC
Contextual Info: 76 CO NNECTIO N DIAGRAM PINOUT A /54/7476 0 / / o / c^ ^S4H/74H76 Gf / ci 7 ^ 54LS/74LS76£ v / 6 / 6 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks DESCRIPTION — The ’76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip-flop.

Contextual Info: Alle Rechte vorbehalten/ M l rights re strni 5 4 2 3 1 C r i m p i n g of AWG 2 4 - 2 8 : hand t o o l 09 99 000 0501 and l o c a t o r 09 99 000 0531 Dal. Detail. 12apr2010 5000 100 B ulk packaging 09 67 000 7476 580 PL1 losp. 09 67 000 7475 580 S4 Stand.

T308

Abstract: DT 8210 IC EUPEC T1059 IC 7476 EUPEC T 1078 F t348 EUPEC T 218 N 12 T1258 EUPEC t 1209 EUPEC T 508
Contextual Info: EUPEC Phase control thyristors Type V drm Itrm sm nE Itsm » • 34035^7 00DQ1D3 11T ■ UPEC / i2dt Itavm/Ic V TC> it (di/dt)cr (dv/dt)cr V gt 1er Rthjc V rrm V A F Z S -O I 10 ms, 10 ms, tv, tvj max 180 “el sin. tv, - ^vj max tv, max tv, max □IN typ.

7476 J-K Flip-Flop

Abstract: TTL 7474 J-K Flip-Flop 7476 Flip-Flop 7470 7472 Flip-Flop 7476 ttl 7474 D flip-flop 7476 7473 dual JK 7470 TTL
Contextual Info: Digital Integrateci Circuits T T L Flip-F lops A range o f standard '7 4 0 0 series' T T L flip -flo p s is available in plastic dual-in-line encapsulation. D IC 7470 D.C.CIocked J— K F lip -F lo p D IC 7472 J— K Master-Slave F lip -F lo p DIC 7473 D U A L J— K Master-Slave F lip -F lo p

7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Contextual Info: SN547G, SN54LS76A, SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR D EC EM BE R 1 9 8 3 -R E V IS E D M A R C H • Dependable Texas Instruments Quality and Reliability TO P V IE W ] *^16 : i k iclkC 15 H 1 Q 1 prëC 2 14 : i q 1clrC 3 13 DGND

LTT thyristor

Abstract: 7476 KA 3845
Contextual Info: Z&texe Power S em icon du ctor Devices U ltra H ig h P o w e r L ig h t T rig g ered T h y risto rs (LTT F e a tu r e s • I m p o r te d th e p ro d u c tio n te c h n o lo g y • L ig h t trig g e r e d th y r i s t o r w ith in te g r a te d o v e r-v o lta g e p ro te c tio n

EUPEC DIODE

Abstract: A198S
Contextual Info: EUPEC blE » • 3HD3ET7 □□□133D TT7 ■LIPEC dv/dt cr Vgt Igt RthJC DIN DIN tvj = tv) = 180 °el I EC 747-6 I EC 747-6 25 °C 25 “C sinus F a s t a s y m m e tr ic th y ris to rs Type A 198 S A 358 S "f-.'j max 10 ms, t j| max sin. ‘vi = tvi =

EUPEC T1059

Abstract: EUPEC t 1209 t308 T86N EUPEC T 1078 F TV 955 200 20
Contextual Info: Type V drm It r m s m 4TE It s m » • 3403^7 /i2dt Itavm/Ic 1 EU P E C P h a s e control thyristors a O D n iD 3 U T ■ UPEC it di/dt cr 1q (dv/dt)cr Vgt typ. D IN tVj = I E C 7 4 7 -6 2 5 “C v in s V 2 "P Z J5 -O I Rthjc tv j m a x Outline d 11 K/W

T 358 N 1600

Abstract: t 250 n 1200 245000 IC 7476 T31N
Contextual Info: EUPFC Phase control thyristors V d sm V rsm It r m sm V drm = Vrrm + 100 V V A Itsm /¡2dt Itavm/Ic 10 ms, 10 ms, tvj max tvj max 180 °el sin. A A2s A/°C di/dt cr (dv/dt)cr Vgt Ig t RthJC t»i = tvj max DIN typ. IEC 747-6 DIN IEC 747-6 tvj = 25 °C tvj =

T188F

Abstract: T510S T-290 eupec
Contextual Info: EUPEC F as t thyristors Type V drm V It r m s m It s m / i2dt 10 ms, tj max kA A2s D • 3 4 Q 3 S t17 D0G13SÖ di/dt cr (dv/dt)cr tv j max DIN IEC 747-6 Itavm/Ic V(TO) rT 10 m s, 1 80 "Bl tv | = t,j = tv , max s in . t ’.'i max E4T ■ U P E C V gt Iq t

17N800

Abstract: 130 N 300 t 250 n 1200 t 345
Contextual Info: Phase control thyristors Type It r m s m V drm It s m /i2dt Itavm/Ic V TO It (di/dt)cr tvi max Outline (dv/dt)cr V gt 1er R thJC DIN IEC 747-6 tVj = 25°C tvj = 25°C sinus V/us V mA °C/W °C V rrm V d sm V r sm =Vdrm =V r r m + 100 V V A 10 ms, 10 ms, I8 0 °e l

dt61n

Abstract: dt250n DT18N td18n
Contextual Info: EUPEC MIE D • 3MD35T7 DOGDiaD STI ■ Thyristor-diode-modules for current source inverters Type Vdrm Vrrm TRM SM dv/dt cr ^ th J C yp- DIN EC 747-6 180 °el sin. ns V/flS 50 100 di/dt)cr /'i2dt tavm/Ic 10 ms, 10 ms, VJ V] max 180 °el sin. VJ = v] max vj max

Contextual Info: A Table Of Contents ^Arrays Pages Pin Grid Arrays / Zero Insertion Force PG A/ZIF PG A/ZIF PG A/ZIF Open top PG A/ZIF (Interstitial) PGA / ZIF (Open Top, Interstitial) NP89 NP161 NP171 NP236 NP178 9-10 11-12 13-14 15-16 17-18 IC264 NP276 19 20-21 Ball Grid Arrays

IC 7476

Abstract: features of ic 7476 applications IC 7476 of Ic 7476 transistor 076 7476 ic
Contextual Info: 2N2857XCSM HIGH FREQUENCY NPN TRANSISTOR IN A HERMETICALLY SEALED CERAMIC SURFACE MOUNT PACKAGE FOR HIGH RELIABILITY APPLICATIONS MECHANICAL DATA Dimensions in mm inches 1.02 ± 0.10 (0.04 ± 0.004) 0.51 ± 0.10 (0.02 ± 0.004) 0.31 rad. (0.012) • SILICON NPN TRANSISTOR