74191 COUNTER Search Results

74190 counter

Abstract: ttl 74190 74191 8 bit 74190 ttl 74191 74191 74191 state diagram counter 74190 74191 logic diagram 74191 counter
Contextual Info: TTL/MSI 93190/54190, 74190 93191/54191, 74191 UP/DOWN DECADE AND BINARY COUNTER DESCRIPTION - The 93190/54190, 74190 and 93191/54191, 74191 are Synchronous U p/ Down Counters w ith enable co n tro l presetting fa c ility , single line u p /dow n co n tro l, cascading

pin diagram of ic 74190

Abstract: ic 74190 pin diagram of ic 74191 logic diagram of ic 74191 f ic 74190 counter 74190 and pin diagram of IC 74190 Synchronous and Ripple Counters of IC 74191 pin diagram of ic 74ls191
Contextual Info: 74190, 191, LS191 Signetics Counters '190 Presettable BCD/Decade Up/Down Counter '191 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74190 25MHz 65mA 74191 25MHz 65mA 74LS191

Truth Table 74191

Contextual Info: 191 CONNECTION DIAGRAM PINOUT A 54/74191 6 54LS/74LS191 l UP/DOWN BINARY COUNTER With Preset and Ripple Clock DESCRIPTION— The '191 is a reversible modulo-16 binary counter fea­ turing synchronous counting and asychronous presetting. The preset feature

74LS190 PIN diagram

Abstract: presettable digital clock ttl 74191 Fairchild 74190 74LS191 74155 D130 74192 74ls192 pin diagram of 74163
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

Truth Table 74191

Abstract: 74191 truth table 74191 The truth table 74191 state diagram 74LS191 up down counter truth table
Contextual Info: NATIONAL SENICOND -CLO GIO 02E D I bSD112B □D b B 'in 7 I 191 CONNECTION DIAGRAM j PINOUT A 54/74191 54LS/74LS191 P i[T q UP/DOWN BINARY COUNTER T ^ cp c e [T 751 rc ö/d |T 12] T C 02 [? Ï Ï J 'P L 03 U Î^ P 2 g n d HIGH SPEED — 30 MHz TYPICAL COUNT FREQUENCY

SS501

Abstract: LS190 LS191 131-6 RJ 4 nts 5d-11 SN54190 SN54191 SN54LS190 T-13-L SN74190
Contextual Info: SDLS072 SPJ54190, S N 54191, SN54LS190, SN54LS191, SN74190, SN 74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWNiUP MODE CONTROL D E C E M B E R 1 9 7 2 — RE V IS E D M A R C H 1 9 8 8 Counts 8-4-2-1 BCD or Binary S N 54 1 9 0. S N 54 1 9 1, SN 54LS190.

ic 74190

Abstract: 74190 74191 counter 74191 74LS190 74190 counter m7 hc 08 counter 74190 Scans-00106469 74LS19I
Contextual Info: — 150 — 74191 Presetable Synchronous U p /D o w n Binary Counter INPUTS OUTPUTS INPUTS * * SI n A * N LS ALS fraax CLK 20 20 30 80 85 16 16 MHz tw n n CLK 25 25 16.5 6 4 .0 33 33 ns tw Dn LOAD 35 35 20 6 1.0 25 28 ns tsu 0 n DATA 20 T 20 T 20 T 8T 2 .5

Truth Table 74191

Abstract: 74191 The truth table pin diagram of 74LS191 74191 truth table 74191 logic diagram 74191 state diagram 74191 74LS191 pins 74LS191PC 74LS191FC
Contextual Info: 191 C O N N E C T IO N D IA G R A M PIN O U T A 54/74191 6 ^4L S /74LS 191 p i|T / UP/DOW N BINARY COUNTER W ith Preset and Ripple Clock D E S C R IP T IO N — T he '191 is a reve rsib le m o d u lo -1 6 b in a ry c o u n te r fe a ­ tu rin g s y n c h ro n o u s c o u n tin g and a s ych ro n o u s p re se ttin g . T h e p reset fe a ture

20t201

Abstract: ic 74190 74190 74191 74191 8 bit counter 74190 f ic 74190 BCD counter IC 74LS190 74190 counter
Contextual Info: - 149 - Presettable synchronous Up/D ow n BCD Counter 74190 A CLOCK CLOCK At ENABLE DOWN/ < OUTPUTS INPUTS o 4 bit ib im ä t y - r r <7 -9 u /d -w i y io 9 ') T S i i ' L o ffi)H £ lc o v > T lil6 0 « * # » . m ff » M n n Load D/ Ü H L H H CK m n -

SN74191

Abstract: SN54190 SN54191 SN74190 SN74190 counter
Contextual Info: TTL MSI CIRCUIT TYPES SN54190, SN54191, SN74190, SN74191 SYNCHRONOUS UP/DOW N COUNTERS WITH DOW N/UP MODE CONTROL C IR C U IT TYPES S N 5 4 1 9 0 , S N 5 4 1 9 1 , S N 7 4 1 9 0 , S N 7 4 1 9 1 B U L LE TIN NO. DL-S 7 0 1 1 3 8 4 , SEPTEM BER 1 9 7 0 J O R N D U A L - IN - L IN E

74LS191 pins

Abstract: 74190 TTL 74190 74ls191 function table 74191 state diagram signetics 74190 74190 counter LS191 counter 74190 74LS191
Contextual Info: Signefics 74190, 191, LS191 Counters '1 9 0 P resettable B C D /D e c a d e U p /D o w n C o un ter '191 P resettable 4-Bit Binary U p /D o w n C o un ter Product Specification Logic Products FEATURES • Synchronous, reversible counting • BCD/decade— '190

ci 74190

Abstract: counter 74190 ci 74191 74190 74191 counter ttl 74191 74191 state diagram signetics 74190 74LS191 LS191
Contextual Info: Signetics 74190, 191, LS191 Counters '190 Presettable BCD/Decade Up/Down Counter '191 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES • Synchronous, reversible counting • BCD/decade— '190 4-bit binary— '191 • Synchronous, reversible counting

74190

Abstract: 74LS191 pins ttl 74190 counter 74190 signetics 74190 74191 state diagram 74ls191 function table
Contextual Info: 74190, 191, LS191 Signetics Counters '190 Presettable BCD/Decade Up/Down Counter '191 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES • Synchronous, reversible counting • BCD/decade—'190 4-bit binary—'191 • Synchronous, reversible counting

STR W 5453 A

Abstract: STR 5453 STR W 5453 STR W 5453 C Truth Table 74190 Truth Table 74192 74193 truth table truth table 7454 str w c 5453 Truth Table 74193
Contextual Info: TTL/MSI 9393/5493, 7493 4 -B IT BINARY COUNTER D E S C R IP T IO N -T h e T T L /M S I 9393/5 4 9 3 , 7493 is a 4-Bit Binary Counter consisting of four master/ slave flip-flops which are internally interconnected to provide a divide-by-two counter and a divide-by-eight counter. A gated direct reset line is provided which inhibits the count inputs and

ttl 74191

Abstract: 74LS191M
Contextual Info: • ■ ■ SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL ■ D E C E M B E R 1 9 7 2 - R E V I S E D M A R C H 1 9 8 8

7483 4 bit binary full adder

Abstract: 74151 demultiplexer 74153 full adder 74198 shift register 7483 4 bit binary adder 7483 8 bit binary adder 74155 demultiplexer 74150 multiplexer bcd adder with 74283 4 bit 7483 binary adder
Contextual Info: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (MHz) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL 54/7442 BCD-to-Decimal Decoder 22 140 X 54/7443 Excess 3-to-Decimal Decoder 22 X X 54/7444 Excess 3 Gray-to-Decimal Decoder

74LS190 pins

Abstract: 74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins Synchronous 74163 74LS161 74160 74LS162 74LS191 pins
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L-T T L D121 54/7490A, 54LS/74LS90 D122 54/7492, 74LS92 D123 S4/74293, 54LS/74LS293 6 7 141 Vcc = Pin 5 GND = Pin 10 N C = Pin 4,13 - Vcc = Pin 5 GND = Pin 10 N C = 2, 3, 4, 13 D124 S4/7493A, 54LS/74LS93 D125 54/74176, 54/74177,

74LS160

Abstract: Synchronous 74163 74LS190 pins 74192 74LS193 74LS192 pins 74LS191 pins Fairchild 74190 D129 93S16
Contextual Info: FAIRCHILD DIGITAL TTL I Max Clock Rate MHz Typ Clock to Q Output Delay-ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Synchronous 93L16 16 Presettable S _r 23 26 85 D127 4L,7B,9B 2 \/ Synchronous 93S16 1/ 16 Presettable S _r 90

74162

Abstract: D129 74LS191 74192 pin diagram of 74163 74160 pin 74190 74LS162 74LS190 pins presettable digital clock
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 5 D85 54LS/74LS373

Contextual Info: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (M H z ) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL DD 54/7442 BC D -to-D e cim al Decoder 22 140 X X 54/7443 Excess 3-to-Decim al Decoder 22 140 X X X 54/7444

74194 shift register

Abstract: 74377 register logicaps shift register by using D flip-flop 7474 74191 counter 74377 Latches 74373 altera logicaps TTL library 74374 74373 ttl 74191
Contextual Info: €Pßl400 PROGRAMMABLE BUS PERIPHERAL FEATURES GENERAL DESCRIPTION • Bus I/O —Register Intensive Buster EPLD The EPB1400 (Buster) EPLD from Altera repre­ sents the firs t M icro proce ssor Peripheral UserConfigurable at the Silicon level. The device consists

Contextual Info: FUNCTIONAL SIMULATOR PLFSI M FEATURES GENERAL DESCRIPTION • Functional Simulation for Altera’s entire family of EPLDs. PLFSIM, the Altera Functional Simulator, provides a convenient and easy-to-use tool for testing the logical operation of any EPLD design. This software

FZH115B

Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
Contextual Info: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P

pin diagram of ic 74190

Abstract: 74LS191n ic 74190 pin diagram of ic 74191 74191n 74190N f ic 74190 74191 logic diagram logic diagram of ic 74191 pin diagram of ic 74ls191
Contextual Info: 74190, 191, LS191 Signefics Counters '190 Presettable BCD/Decade Up/Down Counter '191 Presettable 4-Bit Binary Up/Down Counter Product Specification Logic Products FEATURES • Synchronous, reversible counting • BCD/decade— '190 4-bit binary— '191 • Synchronous, reversible counting