6FEB2006 Search Results

LMX2351

Abstract: 31257*E 312265ED
Contextual Info: LMX2531 High Performance Frequency Synthesizer System with Integrated VCO General Description Features The LMX2531 is a low power, high performance frequency synthesizer system which includes a fully integrated deltasigma PLL and VCO with fully integrated tank circuit. The third

TI QFN marking

Abstract: A115-A C101 SN74AUC17
Contextual Info: SN74AUC17 HEX SCHMITT-TRIGGER BUFFER www.ti.com SCES497A – OCTOBER 2003 – REVISED MARCH 2005 FEATURES • VCC 1 14 2 13 6A 3 12 6Y 4 11 5A 5 6 10 5Y 9 4A 7 8 4Y • • • • • 1Y 2A 2Y 3A 3Y 1A • RGY PACKAGE TOP VIEW Optimized for 1.8-V Operation and Is 3.6-V I/O

SNJ54HC365

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2006 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-86812012A ACTIVE LCCC FK 20 1 TBD Call TI N / A for Pkg Type 5962-8681201EA ACTIVE CDIP J 16 1 TBD

Contextual Info: DAC7742 DAC 774 2 SBAS256 – DECEMBER 2002 16-Bit, Single Channel DIGITAL-TO-ANALOG CONVERTER With Internal Reference and Parallel Interface FEATURES DESCRIPTION ● LOW POWER: 150mW Maximum ● +10V INTERNAL REFERENCE ● UNIPOLAR OR BIPOLAR OPERATION ● SETTLING TIME: 5µs to ±0.003% FSR

Contextual Info: OPA4243 OPA ® 424 3 OPA ® 424 3 For most current data sheet and other product information, visit www.burr-brown.com Quad OPERATIONAL AMPLIFIER MicroPOWER, Single-Supply FEATURES DESCRIPTION ● MICRO-SIZE, TSSOP PACKAGE ● SINGLE-SUPPLY OPERATION The OPA4243 is a four-channel op amp specifically

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: PT5071—12V 1.5 Amp, 12V Step-Up/Step-Down Integrated Switching Regulator SLTS139 Revised 2/7/2001 Features Description • Single-Device: +12V Output, 7-16V Input • 84% Efficiency • 14-Pin Excalibur Package • Output Current Limit • Adjustable Output Voltage

Contextual Info: TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 4.25 Gbps Cable and PC Board Equalizer FEATURES APPLICATIONS • • • • • • • • • • • • • Multi-Rate Operation Up To 4.25 Gbps Compensates Up To 12 dB Loss At 2.1 GHz Suitable To Receive 4.25-Gbps Data Over Up

Contextual Info: SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J-K FLIP-FLOPS WITH CLEAR SDLS036 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN74SSTVF16859 13ĆBIT TO 26ĆBIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 D Member of the Texas Instruments D D D D D D D D D D D D D D DGG PACKAGE TOP VIEW Widebus Family Operates at 2.3 V to 2.7 V for PC1600,

A115-A

Abstract: AHCT86 SN54AHCT86 SN74AHCT86 SN74AHCT86N SN74AHCT86RGYR
Contextual Info: SN54AHCT86, SN74AHCT86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS250M – OCTOBER 1995 – REVISED JULY 2003 D Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT86 . . . J OR W PACKAGE SN74AHCT86 . . . D, DB, DGV, N, NS,

CD54ACT86

Abstract: CD54ACT86F3A CD74ACT86 CD74ACT86E CD74ACT86M CD74ACT86M96
Contextual Info: CD54ACT86, CD74ACT86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCHS322 – JANUARY 2003 D D D D D D CD54ACT86 . . . F PACKAGE CD74ACT86 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption

A115-A

Abstract: C101 SN54AHCT74 SN74AHCT74
Contextual Info: SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263N – DECEMBER 1995 – REVISED JULY 2003 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLK 1PRE 1Q 1Q 14 1D 1 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE

MAX222

Abstract: MAX222CDW MAX222CDWR MAX222CN MAX222IDW MAX222IN
Contextual Info: MAX222 5ĆV DUAL RSĆ232 LINE DRIVER/RECEIVER WITH ±15ĆkV ESD PROTECTION SLLS590D − SEPTEMBER 2003 − REVISED AUGUST 2004 D ESD Protection for RS-232 Bus Pins D D D D D D D DW OR N PACKAGE TOP VIEW − ±15-kV Human-Body Model Meets or Exceeds the Requirements of

PT78ST115V

Contextual Info: PT78ST100 Series 1.5 Amp Positive Step-Down Integrated Switching Regulator SLTS059A Revised 6/30/2000 • • • • • • • Very Small Footprint High Efficiency > 85% Self-Contained Inductor Internal Short-Circuit Protection Over-Temperature Protection

Contextual Info: SN74LV541AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES573A – JUNE 2004 – REVISED AUGUST 2005 FEATURES • • Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model A114-A

Contextual Info: PT6650 Series 5-A 12 /24-V Input Adjustable Integrated Switching Regulator SLTS038B -FEBRUARY 1999 - REVISED MARCH 2004 Features • • • • • • • Single Device: 5-A Output Input Voltage Range: 9 V to 28 V 12 V / 24 V Input Compatible Adjustable Output Voltage

Contextual Info: PT6100 Series 1 Amp Adjustable Positive Step-down Integrated Switching Regulator SLTS029A Revised 6/30/2000 • • • • • • • 90% Efficiency Adjustable Output Voltage Internal Short Circuit Protection Over-Temperature Protection On/Off Control (Ground Off)

Contextual Info: TMP175 TMP75 SBOS288H − JANUARY 2004 − REVISED SEPTEMBER 2005 Digital Temperature Sensor with Two-Wire Interface FEATURES D 27 ADDRESSES TMP175 8 ADDRESSES (TMP75) D DIGITAL OUTPUT: Two-Wire Serial Interface D RESOLUTION: 9- to 12-Bits, User-Selectable

5962-87804012A

Abstract: 5962-8780401CA 5962-8780401DA SN54ALS21A SN54AS21 SN74ALS21A SN74AS21
Contextual Info: SN54ALS21A, SN54AS21, SN74ALS21A, SN74AS21 DUAL 4-INPUT POSITIVE-AND GATES SDAS085B – APRIL 1982 – REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

A115-A

Abstract: C101 SN54AHC86 SN74AHC86
Contextual Info: SN54AHC86, SN74AHC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCLS249I – OCTOBER 1995 – REVISED JULY 2003 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHC86 . . . J OR W PACKAGE SN74AHC86 . . . D, DB, DGV, N, NS, OR PW PACKAGE

SN54ABTH32318

Abstract: SN74ABTH32318 SN74ABTH32318PN SN74ABTH32318PNG4
Contextual Info: SN54ABTH32318, SN74ABTH32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180E – JUNE 1992 – REVISED MAY 1997 D D D D D Members of the Texas Instruments Widebus+  Family State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation

A115-A

Abstract: C101 SN54LV244A SN74LV244A SN74LV244ADW SN74LV244ARGYR
Contextual Info: SN54LV244A, SN74LV244A OCTAL BUFFERS/DRIVERS WITH 3ĆSTATE OUTPUTS SCLS383L − SEPTEMBER 1997 − REVISED APRIL 2005 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 1 20 2Y4 1A1 1OE VCC VCC VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1

AC112

Abstract: AC112M CD54AC112 CD54AC112F3A CD74AC112 CD74AC112E CD74AC112M CD74AC112M96
Contextual Info: CD54AC112, CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS325 – JANUARY 2003 D D D D D D CD54AC112 . . . F PACKAGE CD74AC112 . . . E OR M PACKAGE TOP VIEW AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the