64KX4 Search Results

Contextual Info: P U E L M M A m in t e i C 1P O C Q L LOW POWER 64Kx4 CHMOS DYNAMIC RAM 51C259L-12 120 0.1 Maximum Access Time ns Maximum CHMOS Standby Current (mA) 51C259L-15 150 51C259L-20 200 0.1 0.1 • TTL And HC Compatible Low Power Data Retention - Standby current, CHMOS — 100 /iA

Contextual Info: 64KX4 BASED Dense-Pac Microsystems, inc. C M O S SRAM FAM ILY DESCRIPTION: The Dense-Pac 64K X4 Based Fam ily consists of static ra n d o m a c c e s s m e m o rie s S R A M S o rg a n iz e d as described below. T h ese m em ories are ideally suited for use in large

Contextual Info: ^ED I EDI8M1665C Electronic D«*igrtt Inc. High Speed Megabit SRAM Module 64Kx16 CMOS, High Speed Programmable, Static RAM Module Features The EDI8M1665C is a 1024K-bit high speed CMOS Static RAM Module consisting of four 4 64Kx4 Static RAMs in leadless chip carriers surface-mounted onto a

Contextual Info: i 'A I W H IT E / M I C R O E L E C T R O N I C S 64Kx4 SRAM W P S 64K 4- X S J X PRELIMINARY* PLASTIC PLUS FEATURES • Access Times 15,17, 20nS PIN C O N FIG U R A T IO N TO P VIEW ■ Standard Commercial Off-The-Shelf COTS Memory Devices for Extended Temperature Range

Contextual Info: _ EDI8466CA ^ ED I Electronic D e ig n s Inc. High Speed Monolithic 256K SRAM niF@M^TD i 64Kx4 Static RAM CMOS, High Speed Monolithic Features The EDI8466CA is a high performance CMOS Static RAM organized as 65,536 locations x 4 bits. The EDI8466CA offers an Output Enable function GS for

Contextual Info: K6E0804C1E-C CMOS SRAM Document Title 64Kx4 Bit with OE High Speed Static RAM(5V Operating). Revision History Rev No. History Rev. 0.0 Initial release with Preliminary. Aug. 1. 1998 Preliminary Rev. 1.0 Release to Final Data Sheet. Nov. 2. 1998 Final Draft Data

V53C464

Abstract: WJ 66 scr
Contextual Info: Nf VITEUC V53C261 FAMILY HIGH PERFORMANCE LOW POWER 64KX4 MULTIPORT VIDEO MEMORY WITH FAST PAGE MODE V V53C261 10 12 Max. RAS Access Time, tRAC 100 ns 120 ns Max Column Address Time, (trA A ) 45 ns 55 ns HIGH PERFORMANCE V53C261 Min. Fast Page Mode Cycle Time, (tp c )

Contextual Info: Q S86442 High-Speed CMOS 64Kx4 Cache TAG RAM Q QS86442 ADVANCE INFORMATION FEATURES/BENEFITS Fast Match and Access times • Access time of15ns/20ns/25ns/35ns Commercial • Match time of 15ns/20ns/25ns/35ns Commercial • Low power, high-speed QCMOS technology

Contextual Info: KM64258C CMOS SRAM 64Kx4 Bit With OE High Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 12, 15, 20 ns (Max.) • Low Power Dissipation Standby (TTL) : 40 mA (Max.) (CMOS) : 2 mA (Max.) Operating KM64258C-12 : 150 mA (Max.) KM64258C-15 :140 mA (Max.)

Contextual Info: PRELIMINARY KM64258E CMOS SRAM Document Tills 64Kx4 Bit with OE High Speed Static RAM(5V Operating), Evolutionary Pin out. Revision History RevNo. History Rev. 0.0 Initial draft Draft Data Aug. 1 .1 9 9 8 Remark Preliminary The attached data sheets are prepared and approved by SAM SUNG Electronics. SAM SUNG Electronics CO., LTD. reserve the right

64kx4 DRAM

Abstract: marking WMM IC-012 MT42C4064 T-46 00024B1 TS PQ4 24
Contextual Info: MICRON TECHNOLOGY INC 3ÔE D . li^ .i m blllSM^ 000247b b IMRN r~EV ¿ -2 3 - 3 ? n if i» g is is g l ¿ •ù -i 64Kx4 DRAM WITH 256 X 4 SAM VRAM • • • • Industry standard pinout, tim ing and functions H igh performance CMOS silicon gate process

F16K

Abstract: 7306
Contextual Info: QS7306 Q 64K x 4 Ultra Deep FIFO Memory Q S7306 ADVAN CE INFORMATION F E A TU R E S /B E N E FIT S • • • • • 64Kx4 Ultra Deep FIFO Reversible A to B or B to A OE control pin 1/2,1/4, 1/16,1/32 status flags Directly cascades with another UD FIFO

Contextual Info: QS7316 Q 64K x 4 Ultra Deep Burst Mode Dual Port RAM QS7316 ADVANCE INFORMATION FE A TU R E S /B E N E FIT S • • • • • 64Kx4 Ultra Deep Dual Port Allows simultaneous access on both ports 4 cycles first read access, 1 cycle burst read access All operations occur on rising edge of clock

IMS1820E-25

Abstract: IMS1820M IMS1820P-25 IMS1820S-25 IMS1820W-25
Contextual Info: IMS1820 CMOS High Performance 64K x 4 Static RAM m o s D ESC R IPTIO N FE ATU R E S The IN M O S IM S1820 is a high perform ance 64Kx4 C M O S Static RAM. The IM S 1820 allows speed enhance­ m ents to existing 64K x 4 applications w ith the additional benefit of reduced pow er consum ption .

Contextual Info: EDI8F1665C ^EDI B*ctronfc Designs In c." High Speed Megabit SRAM Module ILOMÔMÂiaV 64Kx16 Static RAM CMOS, High Speed Module Features The EDI8F1665C is a high speed 1 megabit Static RAM module organized as 64Kx16. This module is constructed from four 64Kx4 Static RAMs in SOJ packages on an epoxy

EDI8465C35

Contextual Info: ^EDI _ EDI8465C Electronic D«*lgro Inc. High Speed 256K Monolithic SRAM 64Kx4 Static RAM CMOS, High Speed Monolithic Features The EDI8465C is a high speed CMOS Static RAM organized as 64Kx4. Inputs and outputs are TTL compatible and albw for direct interfacing with common system bus architecture.

Contextual Info: ^ E D I EDI8F2465C B«ctronle D#$Jgn* In e ." High Speed 1.5 Megabit SRAM Module UDDM 64Kx24 Static RAM CMOS, High Speed Module Features The EDI8F2465C is a high speed 1.5 megabit Static RAM module organized as 64Kx24. This module is con­ structed from six 64Kx4 Static RAMs in SOJ packages on an

uPD23C4000

Abstract: 93c46 atmel sony Cross Reference atmel 93c66 HN62404P 93C46L rom at29c010 Hitachi SRAM cross reference x2864a UPD23C2000
Contextual Info: MEMORY ICs CROSS REFERENCE GUIDE 3. C R O S S REFEREN CE GUIDE 3.1 Video RAM Density 256K 512K Feature Minimum Organization 64Kx4 Samsung KM424C64 Minimum 64Kx8 KM428C64 Minimum 256KX4 KM424C256 Micron Hitachi Ti HM53461 2 TMS4461 HM534251 TM S44C250 TC524256A

Contextual Info: QS86440 High-Speed CMOS 64Kx4 SRAM with Common I/O Q Q S86440 ADVANCE INFORMATION FEATURES/BENEFITS • High Speed Access and Cycle times • 12ns/15ns/20ns/25ns Commercial • 15ns/20ns/25ns/35ns Military • TTL compatible I/O • Low power, high-speed QCMOS technology

Contextual Info: Q S7316 64K x 4 Ultra Deep Q QS7316 Burst Mode Dual Port RAM in f o r m a t io n FEATURES/BENEFITS 64Kx4 Ultra Deep Dual Port Allows simultaneous access on both ports 4 cycles first read access, 1 cycle burst read access All operations occur on rising edge of clock

Contextual Info: SRAM Test Configuration Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load +5V Figure 1. GNDto 3.0V 3 ns 1.5V 1.5V See Figures +5V Output test loads for: 4Kx4, 16Kx4, 64Kx4, 32Kx8 &128Kx8 SRAMs Except Low-Power

A7 transistor

Contextual Info: QS86447 High-Speed CMOS 64Kx4 SRAM . _ , , . . with Address Latch Q QS86447 IN INFORMATION FE A T U R E S /B E N E F IT S • • • • • High Speed Access and Cycle times 15ns/20ns/25ns/35ns Commercial Common I/O with Output Enable Low power, high-speed QCMOS technology

Contextual Info: SM33264 2MBit 64Kx 32 CMOS Fast SRAM Module General Description Features The SM33264 is a high performance, 2-megabit static RAM module organized as 64K words by 32 bits, in a 64-pin, single-in-line memory module (SIMM) package. The module utilizes eight 64Kx4 high speed static RAMs

Contextual Info: PEELM M kUY 51C258LT LOW POWER 64Kx4 CHMOS DYNAMIC RAM ¡ n te T 51C258L-12 120 0.1 Maximum Access Time ns Maximum CHMOS Standby Current (mA) 51C258L-15 150 0.1 51C258L-20 200 0.1 • Low Operating Current — 50 mA (max.) ■ Low Power Data Retention - Standby current, CHMOS — 100 /iA