64 MACROCELLS Search Results

XCR3064XL

Abstract: CP56 CS48 DS012 PC44 VQ100 VQ44
Contextual Info: R DS017 v1.5 April 19, 2001 XCR3064XL 64 Macrocell CPLD 14 Product Specification Features Description • Lowest power 64 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 145 MHz • 64 macrocells with 1,600 usable gates The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at

CP56

Abstract: CS48 DS012 PC44 VQ100 VQ44 XCR3064XL xcr3064xl vq44
Contextual Info: R XCR3064XL 64 Macrocell CPLD DS017 v1.6 January 8, 2002 14 Product Specification Features Description • Lowest power 64 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 145 MHz • 64 macrocells with 1,500 usable gates The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at

XCR3064XL

Contextual Info: R DS017 v1.4 April 11, 2001 XCR3064XL 64 Macrocell CPLD 14 Product Specification Features Description • Lowest power 64 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 145 MHz • 64 macrocells with 1,600 usable gates The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at

XCR3064XL

Abstract: c4924 CP56 CS48 DS012 PC44 VQ100 VQ44 XCR3064XL-6PC44C XCR3064XL-6VQ44C
Contextual Info: R XCR3064XL 64 Macrocell CPLD DS017 v1.7 April 8, 2002 14 Product Specification Features Description • Lowest power 3V 64 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 175 MHz • 64 macrocells with 1,500 usable gates The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at

Contextual Info: fax id: 6128 CYPRESS CY7C373 UltraLogic 64-Macrocell Flash CPLD FLASH370 fam ily the CY7C373 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Features • 64 macrocells in four logic blocks • 64 I/O pins The 64 macrocells in the CY7C373 are divided between four

Contextual Info: CY7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable™ ISR™ Flash technology — JTAG interface

Contextual Info: 73i CY7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable™ ISR™ Flash technology — JTAG interface

Contextual Info: fax id: 6138 CY7C373Î ^CYPRESS UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

MACH130-20

Abstract: MACH130 MACH230 PAL22V10 PAL26V16
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

Contextual Info: W CYPRESS CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Functional Description Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

PAL26V16

Abstract: MACH130-20 PAL 007 64 macrocells PAL 007 A MACH130 MACH230 PAL22V10 MACH130-20/BXA
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice/Vantis High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

Contextual Info: fax id: 6138 1CY 7C37 3i CY7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C373i UltraLogic 64-Macrocell Flash CPLD Features • Available in 84-pin PLCC and 100-pin TQFP packages • Pin compatible with the CY7C374i • 64 macrocells in four logic blocks • 64 I/O pins Functional Description

Contextual Info: fax id: 6138 CY7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

preset resistor

Contextual Info: fax id: 6138 CY7C373i UltraLogic 64-Macrocell Flash CPLD Features Functional Description • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

ULTRA37000TM

Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C373i UltraLogic 64-Macrocell Flash CPLD Features • Available in 84-pin PLCC and 100-pin TQFP packages • Pin compatible with the CY7C374i • 64 macrocells in four logic blocks • 64 I/O pins Functional Description

Contextual Info: fax id: 6138 CY7C373Ì UltraLogic 64-Macrocell Flash CPLD • Pin compatible with the CY7C374i Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

TAC01

Contextual Info: CY7C343 CYPRESS SEMICONDUCTOR 64-Macrocell MAX EPLD F eatures F unctional D escription • 64 MAX macrocells in 4 LABs The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible

MS1028

Abstract: MACH130-20 MACH130 teradyne lasar MACH230 PAL22V10 mach 1 to 5 from amd MACH Programmer mach 1 family amd PAL26V16
Contextual Info: FINAL COM’L: -15/20 IND: -18/24 Advanced Micro Devices MACH130-15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks

Contextual Info: fax id: 6138 CYPRESS PRELIMINARY CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram m able ISR™ Flash technology

Contextual Info: CYPRESS 64-Macrocell Flash CPLD is designed to bring the ease of use and high performance of the 22V10 to higbdensity CPLDs. Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays

MACH130

Contextual Info: F IN A L COM’L: -15/20 IND: -18/24 MACH130-15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ ■ 4 “PAL26V16” Blocks

Contextual Info: ” / C Y P R E S S C Y 7 < M UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

Contextual Info: fax id: 6138 CY7C373Ì C'i- UltraLogic 64-Macrocell Flash CPLD • Pin compatible with the CY7C374i Features Functional Description • 64 macrocells in four logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology