54H10 Search Results

74H106

Abstract: 54H106 ScansUX995
Contextual Info: FAIRCHILD HIGH SPEED TTL/SSI . 9H106/54H106, 74H106 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS D E S C R IP T IO N - T h e H S T T L /S S I 9 H 1 0 6 /5 4 H 1 0 6 , 7 4 H 1 0 6 is a H igh Speed J K N eg ative Edge T rig g e re d flip - f lo p . T h e y fe a tu re in d iv id u a l J, K ,

121122

Abstract: 74H101 ScansUX995
Contextual Info: FAIRCHILD HIGH SPEED TTL/SSI . 9H101/54H101, 74H101 JK EDGE TRIGGERED FLIP-FLOP WITH AND-OR INPUTS D E S C R IP T IO N — T h e H S T T L /S S I 9 H 1 0 1 /5 4 H 1 0 1 , 7 4 H 1 0 1 is a H igh S peed J K N eg ative Edge T rig g e re d f lip - f lo p . T h e A N D - O R gate in p u ts are

74H103

Abstract: clock schematic ScansUX995 Flip-Flop on off 54H103
Contextual Info: FAIRCHILD HIGH SPEED TTL/SSI • 9H103/54H103, 74H103 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE CLEARS AND CLOCKS DESCRIPTION - The HSTTL/SSI 9H 103/54H 103, 74H 103 is a High Speed JK Negative Edge Triggered flip -flo p . They feature individual J, K,

74H102

Abstract: 10mAVCC ScansUX995
Contextual Info: FAIRCHILD HIGH SPEED TTL/SSI . 9H102/54H102, 74H102 JK EDGE TRIGGERED FLIP-FLOP WITH AND INPUTS DESCRIPTION — The HSTTL/SSI 9H 102/54102, 74H102 is a High Speed JK Negative Edge Triggered flip-flop. They feature gated JK inputs and an asynchronous clear input. The A N D gate inputs are inhibited while the clock input is LOW; when the clock goes H IG H , the inputs are

74H108

Abstract: clock schematic V126 ScansUX995
Contextual Info: FAIRCHILD HIGH SPEED TTL/SSI . 9H108/54H108, 74H108 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE PRESETS AND A COMMON CLEAR AND CLOCK D E S C R IP T IO N — T h e H S T T L /S S I 9 H 1 0 8 /5 4 H 1 0 8 , 7 4 H 1 0 8 is a H igh Speed J K N eg ative Edge Trig g e re d f lip -flo p . T h e y fe a tu re in d iv id u a l J ,K ,

74H10

Abstract: ScansUX994
Contextual Info: FAIRCHILD HIGH SPEED TTL/SSI . 9H10/54H10, 74H10 TRIPLE 3-INPUT NAND GATE SCH EM ATIC DIA G R A M EACH G ATE LOGIC A N D CO NNECTIO N D IA G R A M DIP (TOP VIEW ) F LA TPA K (TOP VIEW ) 14 Ue { 13 12 11 10 9 5rJ rb I GNO L U L ilL U L llU L llL J Positive lo gic: Y = A B C

MC3100

Abstract: MC3005L MC3005F MC3105F MC3105L
Contextual Info: / TRIPLE 3-INPUT "NANO" GATE | V MTTL III MC3100/3000 series MC3105F * MC3005F MC3105L * MC3005L,P 54H10J (74H10J,N) 1 / 3 O F C IR C U IT SHOWN T h is package consists o f th re e 3-in p u t N AN D gates. Each gate m ay b e used as an inverter, o r tw o gates

dy 255

Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
Contextual Info: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the

transistor k49

Abstract: 54H00 74H00 MC1741C MC1741CP1 MCC1741C MCC3000
Contextual Info: LINEAR INTEGRATED CIRCUIT CHIPS G E N E R A L D ESCRIPTIO N M otorola now o ffe rs a very broad selection o f linear integrated c irc u it chips. Am ong the types o f circuits w hich compose the linear fa m ily there are: A . Operational A m p lifie rs B. Voltage Regulators

transistor k49

Abstract: MC1741C MC1741CP1 MCC1741C MCC54H00 MCC74H00 MCC3000
Contextual Info: L IN E A R IN T E G R A T E D C IR C U IT CHIPS G E N E R A L D E S C R IP T IO N M o to r o la n o w o ffe rs a ve ry b ro a d se le c tio n o f lin e a r integ rated c ir c u it c h ip s . A m o n g th e ty p e s o f c ir c u its w h ic h c o m p o se th e lin e a r f a m ily th e re are:

NAND Gate 3-Input 7410

Abstract: 74LS10PC
Contextual Info: 10 CO NNECTIO N DIAGRAMS PINO UT A '''54/7410 ^é4H/74H10 ^54S/74S10 ö / ' o -h? ^ 4 L S /7 4 L S 1 0 ^ / y 7 TRIPLE 3-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0° C to +70° C

Contextual Info: TYPES 54H101, SN74H101 NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND •OR-GATED j- K R E V ISE D DE C EM B ER 1983 SN64H101_ I PA CKAG E Package Options Include Plastic and Ceramic D IP s SN 74H W I_ I OR N PA CKAG E TO P VIEW ! * Dependable Texas Instruments Quality

SN54H103

Abstract: SN74H103 SN54H1
Contextual Info: TYPES 54H103, SN74H103 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR RE V ISE D DE C EM B ER 19B3 SN 5 4 H 1 0 3 . . . J O R W P A C K A G E SN 7 4 H 1 0 3 . . . J OR N P A C K A G E Pa ck age Options Include Plastic and Ceram ic D IP s TOP VIEW

SN74H101

Contextual Info: TYPES 54H101, SN74H101 AND-OR-GATED J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET E V I S E D D E C E M B E R 1983 SN64H101 I PA CK A G E SN74HTO1 I OR N PA CK A G E Package Options Include Plastic and

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

itt 7441

Abstract: transistor fcs 9012 7446 BCD to 7-segment Fairchild dtl catalog Truth Table 74192 7400 quad 2-input NAND gate truth-table 7449 BCD to 7-segment 7483 truth table Motorola Diode 54H01 semiconductors cross reference
Contextual Info: TTL DATA BOOK Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the Numerical Index. If you are trying to choose the best device for your application, consult the

Standard TTL AOI Dual 2-Wide 2-Input

Abstract: of 7400 Series - TTL 54175 LN 5406 CD 5401 C5445 7400 J-K Flip-Flop 4 nand dip 16 supply voltage 30 v
Contextual Info: LANSDALE SEMICONDUCTOR 1 7E D • ' 5 3 h c1AQ3 DG003QÖ T-H3-ÌJ5 7 ■ T - H t r O l - O '! T -V 6 -0 7 -O S ' MAXIMUM RATINGS Rating Supply Voltage - Vcc T '4 S - 2 3 - 0 5 T '^ S -23-13 Value Unit +7.0 Vdc T -W -H Supply Operating Voltage Range 4.5 to 5.5

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

SN7449

Abstract: 54175 SN7401 74L42 SN7437 SN74S40
Contextual Info: Ordering Instructions and Mechanical Data INTEGRATED CIRCUITS MECHANICAL DATA ORDERING INSTRUCTIONS Electrical characteristics presented in this catalog, unless otherwise noted, apply for circuit type s listed in the page heading regardless of package. Except for diode arrays, ECL, and MOS devices, the availability of a circuit function in a

Contextual Info: TQ MAXIMUM RATINGS Rating Value Unit Supply Voltage - Vcc 7.0 V Input Voltage - Vjn 5.5 V Output Voltage - Vout 5.5 V -55 to +125 °C MOTOROLA INTEGRATED CIRCUITS 54H00 Series 74H00 Series Operating Free-Air Temperature Range TTL III circuits comprise a family

CD 76 13 CP

Abstract: 54H108DM 54H108FM 74H108DC 74H108FC 74H108PC
Contextual Info: 108 C O N N E C T IO N DIAGRAM P IN O U T A 54H/74H108 6//^ 7 DUAL JK E D G E -T R IG G E R E D F LIP -F LO P With Separate Sets, A Com m on Clear and Clock K, [7 TTI Vcc ÏT Iso i Qi |T D ESCRIPTION — T h e ’ 108 is a h ig h sp eed J K n e g a tive e d g e -trig g e re d flip ­

CD 76 13 CP

Contextual Info: 108 CONNECTION DIAGRAM PINOUT A 54H/74H108 6 //t>/7 DUAL JK EDGE-TRIGGERED FLIP-FLOP With Separate Sets, A Common Clear and Clock DESCRIPTION — The '108 is a high speed J K negative edge-triggered flipflop. It features individual J , K, and asynchronous Set inputs to each flip-flop