54F189 Search Results

signetics 723

Abstract: cewe cl 48
Contextual Info: 54F189A Signetics 64-Bit TTL Bipolar RAM, Inverting 3-State Objective Specification Military Logic Products FEATURES APPLICATIONS DESCRIPTION • Address access time: 9ns Max • Scratch pad memory • Power dissipation: 4.3mW/bit typ • Buffer memory • Schottky clamped TTL

AD 726

Abstract: 54F189A 16X4 signetics 723
Contextual Info: NAPC/ S IG N E T IC S /n iL IT A R Y EbE D • QGQ2713 ■ 'T .V é Z S - C ff 54F189A Signetics 3 64-Bit TTL Bipolar RAM, Inverting 3-State Objective Specification Military Logic Products FEATURES APPLICATIONS DESCRIPTION • Address access time: 9ns Max

Contextual Info: 54F189,74F189 54F189 74F189 64-Bit Random Access Memory with TRI-STATE Outputs Literature Number: SNOS166A 54F 74F189 64-Bit Random Access Memory with TRI-STATE Outputs General Description Features The ’F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array Address inputs are buffered to minimize

Motorola transistor smd marking codes

Abstract: 7900801CA lm6482a 5962-8993001MIA replacement for 11c90 TRANSISTOR SMD MARKING CODE QA LM311 SMD JM38510/10305BEA LM714h Motorola semiconductor smd marking codes
Contextual Info: N MILITARY / AEROSPACE DESIGN/PROCESS CHANGE NOTIFICATION PCN Nr: 1998 Listing GIDEP Nr: GIDEP Category: Issued: 01/06/98 TRB Nr: This is to advise you that a Design and/or Process Change will be made to the following MIL/AERO product s : Product ID (Description):

74F161 PC

Abstract: 74F163PC 74f500 74f558 74F164PC 74F548PC 74F138d 74F547PC transistor f630 74F253DC
Contextual Info: F a ir c h ild A d v a n c e d S c h o t t k y T L $ 3. HANDLING PRECAUTIONS FOR SEMICONDUCTOR COMPONENTS The follow ing handling precautions should be observed for oxide isolation, shallow junction processed parts, such as FAST or 100K ECL: 1. All Fairchild devices are shipped in conducting foam or anti­

bipolar PROM

Abstract: plhs18p8 S4LS04 82HS641 PLHS18 54175 82s137a 82S191 68172 54F04
Contextual Info: Signetics I Alphanumeric I Index Military Products H LM119 LM124 LM139 Vol. 1 17 Dual Voltage Comparator Vol.2 22 26 26 Low Power Quad Op Amp LM139A Qual Voltage Comparator Qual Voltage Comparator PLC18V8Z Zero Standby Power Universal PAL -Type Device PLC415

54F189

Abstract: 54F189DC F189
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 07/15/98 Last Update Date: 08/24/98 Last Major Revision Date: 07/15/98 54F189-X REV 0A0 64-BIT RANDOM ACCESS MEMORY WITH 3-STATE OUTPUTS General Description The F189 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs

Contextual Info: al Semiconductor August 1995 5 4 F /7 4 F 1 8 9 6 4 -B it R a n d o m A c c e s s M e m o ry w ith T R I-S T A T E O u tp u ts General Description Features The ’F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize

74act3301

Abstract: scl4412 75307 equivalent CD4015 jm38510/05101 DISCO DFG840 JM38510/33903BEA 74lvc3245 JM38510/05101BCA JM38510/34001BCA
Contextual Info: N ENHANCED SOLUTIONS DESIGN/PROCESS CHANGE NOTIFICATION formerly Military & Aerospace Division PCN Nr: 1999 Listing GIDEP Nr: GIDEP Category: Issued: 01/05/99 TRB Nr: This is to advise you that a Design and/or Process Change will be made to the following High Reliability product(s):

Contextual Info: 0> co 9 National Semiconductor 54F/74F189 64-Bit Random Access Memory with TRI-STATE Outputs General Description Features The ’F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are TRI­

54F189DL

Abstract: 54F189FL 54F189LL 74F189 74F189PC 74F189SC 74F189SJ F189 J16A N16E
Contextual Info: 54F 74F189 64-Bit Random Access Memory with TRI-STATE Outputs General Description Features The ’F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array Address inputs are buffered to minimize loading and are fully decoded on-chip The outputs are TRISTATE and are in the high impedance state whenever the

FDC9268

Abstract: FSA2501M FSA2510 fsa2501 FSA2510M smd diode marking code TO3 FSA3130M TRANSISTOR SMD MARKING CODE QA lmc64841 CB0239W-MSP
Contextual Info: N MILITARY / AEROSPACE DESIGN/PROCESS CHANGE NOTIFICATION PCN Nr: 1996 Listing GIDEP Nr: Issued: 23.12.96 GIDEP Category: TRB Nr: This is to advise you that a Design and/or Process Change will be made to the following MIL/AERO product s : Product ID (Description):

54F189DL

Abstract: 54F189FL 54F189LL 74F189PC 74F189SC 74F189SJ F189 J16A N16E 74F189
Contextual Info: General Description Features The ’F189 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are TRI-STATE and are in the high impedance state whenever

Contextual Info: National Semiconductor 54F/74F189 64-Bit Random Access Memory with TRI-STATE Outputs General Description Features The 'F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are TRI­

DIODE 40c

Abstract: 54F189 54F189DLQB 54F189FLQB 54F189LLQB F189
Contextual Info: MILITARY DATA SHEET Original Creation Date: 05/17/96 Last Update Date: 07/30/96 Last Major Revision Date: 05/17/96 54F189-X REV 1A0 64-BIT RANDOM ACCESS MEMORY WITH 3-STATE OUTPUTS General Description The F189 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs

TSMC 0.18 um MOSfet

Abstract: M38510 10102BCA IDT7204L 5962-8768401MQA 0.18um LDMOS TSMC sl1053 TSMC 0.25Um LDMOS UT63M125BB SMD RTAX250S-CQ208 5962-04221
Contextual Info: DSCC Supplemental Information Sheet for Electronic QML-38535 Specification Details: Date: 9/2/2008 Specification: MIL-PRF-38535 Title: Advanced Microcircuits Federal Supply Class FSC : 5962 Conventional: No Specification contains quality assurance program: Yes

Contextual Info: August 1995 Semiconductor & 54F/74F189 64-Bit Random Access Memory with TRI-STATE Outputs General Description Features The ’ F189 is a high-speed 64-bit RAM organized as a 16word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are TRI­