54ALS1 Search Results

Contextual Info: S IM 54ALS1 0 1 0A , SIM 74ALS1 □ 1 0 A TRIPLE 3 INPUT POSITIVE N A N D B U FFE R S D 2 6 6 1 , A P R IL 1 9 8 2 • Buffer Version of 'A LS 10A • Package Outline” Addition Ceramic S N 74A LS 1010A . . . D O R N • -R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S 1 0 1 0 A . . . J PACKAGE

74AS1034

Abstract: LS1034
Contextual Info: TYPES 54ALS1034, SN54AS1034, SN74ALS1034, SN74AS1034 HEX DRIVERS D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 'A S 1 0 3 4 O ffers High Capacitlve-Drive Capability SN 54ALS1034. S N 54A S1034 . . . J PACKAGE SN 74ALS1034, S N 74A S1034 . . . N PACKAGE

74ALS1000

Abstract: SN54ALS1000A
Contextual Info: TYPES 54ALS1000A. SN54AS1000, SN74ALS1000A, SN74AS1000 QUADRUPLE 2-INPUT POSITIVE NANO BUFFERS/DRIVERS 0 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 ' A L S 1 0 0 0 A is a B u ffe r V e r s io n o f SN 54ALS1O O O A, S N 5 4 A S 1 0 0 0 . . . J PA C K A G E

Contextual Info: SN 54ALS100 3A, S N 74 A LS 10 0 3 A Q U AD RUPLE 2 INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS D 2 6 6 1 , APRIL 1 9 8 2 -R E V IS E D M A Y 1 9 8 6 • S N 5 4 A IS 1 0 0 3 A . . . J PACKAGE Buffer Version of 'A LS03B S N 7 4 A L S 1 0 0 3 A . . . D OR N PACKAGE

MPG54ALS163

Abstract: 4 bit synchronous counter
Contextual Info: ^ M O T O R O L A M ilitary 54ALS163 S y n c h ro n o u s 4-Bit B in a ry C o u n te r (With S y n c h ro n o u s C lear) ELECTRICALLY TESTED PER: 54ALS163 AVAILABLE AS: The ALS163 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable M SI building

SN74ALS1243

Abstract: 74als12 74ALS124
Contextual Info: TYPES S N 54A LS 1242, SM 54ALS1243, SN74ALS1242, SN74ALS1243 QUADRUPLE BUS TRANSCEIVERS W ITH 3-STATE OUTPUTS u w u n u ru in « B W « i 2-W a y Asynchronous Communication between Data DECEMBER 1982-REVISED DECEMBER 1983 SN S 4A LS12 4 2 , S N 54A LS 12 4 3

Contextual Info: ^ M O TO RO LA M ilitary 54ALS163 Synchronous 4 -B it Binary C o u n ter (W ith S ynchronous C lear) ELECTRICALLY TESTED PER: 54ALS163 AVAILABLE AS: The ALS163 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable MSI building

74as175

Abstract: texas instruments of ic 74 ls 83 54AS174 IC sn 74 ls 83 54ALS175 54als174
Contextual Info: TYPES SN 54A LS174, SN 54ALS17S, SIU54AS174, SN 54 A S17S SN 74A LS174, SN 74A LS175, SN 74A S 174, SN 74 A S 175 HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR D 2 6 6 1 , APRIL 1 9 8 2 - REVISION DECEMBER 1 9 8 3 'ALS174 and 'A S 174 Contain Six Flip-Flops with

54ALS10A

Abstract: SN54ALS10A SN54AS10 SN74ALS10A SN74AS10
Contextual Info: SN74ALS10A, SN74AS10, 54ALS10A, SN54AS10 TRIPLE 3-INPUT POSITfVE-NAND GATES M A R C H 1 9 8 4 - R E V I S E D M A Y 1986 • • S N 54ALS10A, SN 54AS10 S N 74ALS10A, SN 74AS10 . . Package O p tio n s In clud e P lastic "S m a ll O u tlin e " Packages, C era m ic C hip C arriers,

Contextual Info: O' *I 0j $v W SN 54ALS190 , S N 5 4 A L S 1 9 1 , S N 74 A L S 19 0 , S N 74 A L S 19 1 SYNCHRONOUS 4-BIT UPfDOWN DECADE AN D BINARY COUNTERS D 2 6 6 1 , DECEMBER 1 9 8 2 -R E V IS E D M A Y 1 9 8 6 54ALS190, 54ALS191 . . . J PACKAGE SN74ALS190, SN74ALS191 . . . D OR N p a c k a g e

Contextual Info: MOTOROLA M ilitary 54ALS138 1 -of-8 D e co d e r ELECTRICALLY TESTED PER: 54ALS138 T he 5 4 A L S 1 3 8 is a h igh -sp e ed 1-of-8 Decoder/Demultiplexer. T h is device is ideally suited for h igh -sp e ed bipolar m e m o ry chip select ad d re ss decoding. T h e m ultiple input en ab le s allo w s parallel e x p a n sio n

Contextual Info: M M O T O R O L A M ilita ry 54ALS161 Synchronous 4-Bit Binary Counter (With Asynchronous Clear) ELECTRICALLY TESTED PER: 54ALS161 AVAILABLE AS: The ALS161 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable MSI building

Contextual Info: M MOTOROLA M ilitary 54ALS161 S y n c h r o n o u s 4-Bit B in a ry C o u n te r (W ith A s y n c h r o n o u s Clear) ELECTRICALLY TESTED PER: 54ALS161 AVAILABLE AS: The ALS161 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable M SI building

Contextual Info: SN 54ALS136, SN54AS136, S N 74 A L S 13 6 , S N 74 A S 13 6 Q U AD RUPLE 2 INPUT EXCLUSIVE OR GA TES WITH OPEN COLLECTOR OUTPUTS D 2 8 3 7 , M ARCH 1 9 8 4 -R E V IS E D M A Y 1 9 8 6 S N 54A L S 136, S N 5 4 A S 1 3 6 . . . J PACKAGE Package Options Include Plastic "Sm all Outline"

ALS161

Abstract: PHL12 54ALS161
Contextual Info: M O T O R O LA Military 54ALS161 Synchronous 4 -B it Binary C o u n ter W ith A synchronous C lear M PO /////// ELECTRICALLY TESTED PER: MPG 54 ALS 161 AVAILABLE A S : The ALS161 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable MSI building

74als1004

Abstract: 54ALS1004 SN54ALS1004 1004A 54AS1004A
Contextual Info: 54ALS1004, SN54AS1004A, SN74ALS1004, SN74AS1004A HEX INVERTING DRIVERS D 2 6 6 1 , A P R IL 1 9 8 2 - 'A S1004A Offers High Capacitive-Drive Capability R E V IS E D M A Y 1 9 8 6 SN 54ALS1004, S N 54A S 1004A . . J P AC KAG E S N 7 4 A L S 1 0 0 4 , S N 7 4 A S 1 0 0 4 A . . . D O R N P AC KAG E

74ALS1245

Abstract: 1624T 885s
Contextual Info: SN 54ALS1245A, SN 74A LS1245A OCTAL BUS TRANSCEIVERS WITH 3 STATE OUTPUTS D 2 6 6 1 , DEC EM BE R 1 9 8 2 -R E V tS E D M A Y 1986 S N 5 4 A L S 1 2 4 5 A . . . J P AC K A G E S N 7 4 A L S 1 2 4 5 A . . , D W OR N P AC KA G E 'B id ire c tio n a l Bus T ransce ive rs in H igh-D e nsity 20-P in

LS1623

Contextual Info: T Y P E S SN 54ALS1620 THRU 54ALS1623 S N 74 A LS 16 2 0 THRU S N 74 A LS 16 2 3 OC TAL BUS TRAN SC EIVERS D 2 6 6 1 , D EC EM BER 1 9 8 2 - R E V IS E D D EC EM B ER 19B3 Bus Transceivers in High-Density 20-Pin DIPs and the New Plastic and Ceramic Chip Carriers Packages

T81C

Contextual Info: TEXAS I N S T R {LO G IC } ûï D Ë j| 0 ^ 1 7 2 3 “53B1723 TEXAS ÏNSÏR CLOGIC DOMBbHl 2 81C 42631 54ALS10A, SNS4AS1Ó, SN74ALS10A, SN74AS10 TRIPLE 3-INPUT POSITIVE-NAND GATES M ARCH 1984 —R EV ISED M AY 1986 • • SN 54ALS10A, SN54AS10 . . . J PACKAGE'

193J

Abstract: DM54ALS192J DM74ALS192M DM74ALS192N J16A M16A Scans-004414
Contextual Info: 54ALS192/DM74ALS192/54ALS193/DM74ALS193 S 3 sieinteonductof Corporation P R E LIM INARY 54ALS192/DM 74ALS192/DM 54ALS193/DM 74ALS193 Synchronous Four-Bit Up/Down Counters Dual Clock with Clear G eneral Description The ’ALS192 and ’ALS193 are synchronous, reversible up /

SRG8

Abstract: SN74ALS166 SN54ALS166 parallel to serial conversion
Contextual Info: O' ' ? ; L SN 54ALS166, SN74ALS166 PARALLEL LOAD 8-BIT SHIFT REGISTERS PRODUCT PREVIEW D 2 6 6 1, A P R IL 1 9 8 2 - R E V IS E D M A Y 1986 SN 5 4 A LS1 66 . . . J P A C K A G E S y n c h ro n o u s Lo ad S IM 7 4 A L S 1 6 6 . . . D O R N P A C K A G E •

ALS10A

Abstract: SN54ALS1010A SN74ALS1010A
Contextual Info: SIM 54ALS1 0 1 0A , S N 7 4 A L S 1 0 1 0 A TRIPLE 3 IN P U T PO S ITIVE NAND BUFFERS □ 2 6 6 1 . A P R IL 1 9 8 2 — R E V IS E D M A Y 1 9 8 6 B uffer V ersion o f 'A L S 1 0 A • P ackage O u tlin e " A ddition C eram ic • O p tion s In clude Plastic " S m a ll

74as10

Contextual Info: SN 54ALS1008A, SN54AS1008A, S N 74 A L S 10 0 8 A , S N 74 A S 10 0 8 A QU AD RUPLE 2-INPUT POSITIVE AND BUFFERS/DRIVERS D2661, DECEMBER 1982-REVISED MAY 1986 • • 'ALS1008A is a Buffer Version of 'ALS08 SN54A LS1008A . SN 54A S 1008A . . J PACKA GE S N 7 4 A L S 1 0 0 8 A , S N 7 4 A S 1 0 0 8 A . . . D OR N PACKAGE

74AS168

Abstract: LS-168a
Contextual Info: T Y P E S SN 54ALS168A , SN 54ALS169A , SN54AS168, SN54AS169 S N 74 A L S 16 8 A , S N 74 A L S 16 9 A , S N 74 A S 1 6 8 , A S 7 4 A S 16 9 SYNCHRONOUS 4-BIT UP/DOWN DECADE A N D BINARY COUNTERS D 2 6 6 1 . DEC EM BE R 1 9 8 2 -R E V IS E D DEC EM BE R 1 9 8 3