54LS6 Search Results

SN74LS83

Abstract: SN54LS638 SN54LS639 SN74LS SN74LS638 SN74LS639 LS638
Contextual Info: 54LS638, 54LS639, SM74LS638. SN74LS639 OCTAL BUS TRANSCEIVERS D2636, JANUARY 1981 -REVISED MARCH 1988 Bidirectional Bus Transceivers in HighDensity 20-Pin Packages 54LS638, SN 54LS639 . . . J PACKAGE S N 74LS638. SN 74LS 639 . . . DW OR N PACKAGE TOP VIEW

Contextual Info: LS670 National Semiconductor 54LS670/54LS670/DM74LS670 TRI-STATE 4-by-4 Register Files General Description These register files are organized as 4 words of 4 bits each, and separate on-chip decoding is provided for addressing the four word locations to eithef write-in or retrieve data.

74LS631

Abstract: 74LS630 SN74LS630 54LS630 CB419 LS631
Contextual Info: TYPES 54LS630, 54LS631, SN74LS630, SN74LS631 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D2550, MARCH 1 9 8 0 -R E V IS E D APRIL 1985 TIM 99630, TIM 99631 Detects and Corrects Single-Bit Errors . . JD PACKAGE S N 54LS630, 54LS631 JD OR N PACKAGE

74LS639

Contextual Info: TYPES 54LS638, 54LS639, SN74LS638, SN74LS639 OCTAL BUS TRANSCEIVERS D 2 6 3 6 , J A N U A R Y 1981 - R E V IS E D D E C E M B E R 1983 SN 54LS638, SN 54LS639 . . . J PA CKAGE Bidirectional Bus Transceivers in HighDensity 20-Pin Packages SN 7 4LS 6 38 , SN 7 4LS 6 39 . . . DW , J OR N PA CKA G E

SN74LS630

Abstract: 74LS630 54LS630
Contextual Info: 54LS630, SN74LS630 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D 2550, MARCH 1 9 8 0 -R E V IS E D MARCH 1988 TIM99630 • Detects and Corrects Single-Bit Errors SN 54LS6 30, JD PACKAGE SN 74LS6 30 . . . N PA C K A G E • Detects and Flags Dual-Bit Errors

SN74LS

Abstract: D2636 SN54LS638 SN54LS639 SN74LS638 SN74LS639
Contextual Info: 54LS638, S 54LS639, S N 74 LS 6 3 8 r SN74LS639 O C T A L BUS TR A N S C EIVERS SDLS188 Bidirectional Bus Transceivers in IHighDensity 20-Pin Packages D 2 6 3 6 , JANUARY 1981 -R EVISED MARCH 1988 S N 54LS639. S N 54LS639 . . J PACKAGE S N 7 4 L S 6 3 8 . S N 7 4 L S 6 3 9 . . . D W OR IM P A C K A G E

SN74LS873

Abstract: 54ls674 54LS673 LS674
Contextual Info: 54LS673, 54LS674, SN74LS673, SN74LS674 16-BIT SHIFT REGISTERS 024 21 , MARCH 1985 - REVISED MARCH 1988 S N 54LS673 . . . J OR W PACKAGE SN 74LS673 . . . DW OR N PACKAGE |'LS673 ► 16-Bit Serial-ln, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register

74ls69

Abstract: 54LS68 74LS 219
Contextual Info: 54LS68, 54LS69, SN74LS68, SN74LS69 DUAL 4-BIT DECADE OR BINARY COUNTERS D ECEM BER 1983 - R E V IS E D M A R C H 1 9 8 8 5N 54LS68, SN 54LS69 . . . J PACKAG E S N 7 4 L S 6 8 , S N 7 4 L S 6 9 . . . D OR N P A C K A G E • Heavy Duty Outputs Io l Rated at

Contextual Info: M MOTOROLA M ilita ry 5 4 L S 6 7 0 4 X 4 R egister File W ith 3 -S ta te O utputs MPO mini ELECTRICALLY TESTED PER: M IL-M -38510/31901 The 54LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address

SN74LS630

Abstract: 1N111 SN54LS630 SN54LS631 TIM99630 TIM99631 LS630 SN74LS63 LS631 DB8L
Contextual Info: TYPES 54LS630, 54LS631, SN74LS630, SK74LS631 16-BIT PARALLEL ERROR DETECTION AND CORRECTION CIRCUITS D 2 5 5 0 , M A R C H 1 9 8 0 - REVISED APRIL 1 9 8 5 T IM 9 9 6 3 0 T IM 9 9 6 3 1 D etects and Corrects Single-Bit Errors ID P A C K A G E S N 54LS 630. S N 54LS631

LS688

Abstract: LS682 SN54LS689 SN54LS682 SN74LS682 SN74LS689 133P5 LS686
Contextual Info: TYPES 54LS682 THRU 54LS689, SN74LS682THRU SN74LS689 8-BIT MAGNITUDE/IDENTITY COMPARATORS D 2 6 1 7 r J A N U A R Y 1 9 8 1 - R E V J S E D D E C E M B E R 1983 •• Compares Two 8-Bit Words • Choice of Totem-Pole or Open-Collector Outputs SN 54LS6 82 TH RU S N 5 4 LS6 8 S . . . J PA C K A G E

n75k

Contextual Info: 54LS68, 54LS69, SN74LS68, SN74LS69 DUAL 4-BIT DECADE OR BINARY COUNTERS D ECEM BER 1983 - Heavy Duty Outputs Io l Rated at 8mA/16 mA R E V IS E D M A R C H 1 98 B 5N 54LS68, SN 54LS69 . . . J PACKAG E S N 7 4 L S 6 8 . S N 7 4 L S 6 9 . . . D OR N P A C K A G E

SN74LS604

Contextual Info: 54LS604, 54LS606, 54LS607, SN74LS604, SN74LS606, SN74LS607 OCTAL 2-INPUT MULTIPLEXED LATCHES D254-5, JULY 1979-REVISED MARCH 1988 T IM 9 9 6 0 4 , T IM 9 9 6 0 6 , T IM 9 9 6 0 7 SN 54LS 604, SN 54LS 606, SN 54LS607 . . JO PACKAGE SN 74LS 604, SN 74LS 606. SN 74LS607 . . . JD OR N PACKAGE

SN74LS620

Contextual Info: 54LS620, 54LS621, SN74LS620, SN74LS621, SN74LS623 OCTAL BUS TRANSCEIVERS D 2 5 3 7 , A U G U S T 1 9 7 9 - R E V IS E D M A R C H 1 9 8 8 Bidirectional Bus Transceivers in High-Density 20-Pin Packages S N 54LS 620, SN 54LS621, S N 5 4 L S 6 2 2 . . . J P AC KA G E

SN74LS620

Abstract: 5161ag D2537 SN74LS621 51712 A1725 SN74LS623 LS621
Contextual Info: 54LS62Q , SNS4LS621, S N 7 4 L S 6 2 0 , S N 74LS G 21, S N 74L S 623 OCTAL BUS TRANSCEIVERS S D LS 185 D 2537, AUGUST 1 9 7 9 -R E V IS E D MARCH 1980 S N 54LS 620, SN 54LS621. B idirectional Bus Transceivers in H igh-Density 20-Pin Packages S N 54 L S 6 2Z . . . J PACKAGE

74LS series logic gates 3 input or gate

Abstract: DM74LS670 74LS series logic gates 54LS 54LS670 54LS670DMQB 54LS670FMQB 54LS670LMQB 74LS DM54LS670
Contextual Info: 54LS670 54LS670 DM74LS670 TRI-STATE 4-by-4 Register Files General Description These register files are organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data

Contextual Info: 54LS670, SN74LS670 4-BY-4 REGISTER FILES WITH 3-STATE OUTPUTS BULLETIN NO DL-S 7612122, MARCH 1974 - REVISED MARCH 1988 Separate Read/W rite Addressing Permits Simultaneous Reading and Writing . J OR W PACKAGE . D OR N PACKAGE SN 54LS670 SN 74LS670 TOP VIEW

54LS630

Abstract: SN74LS630 74LS630
Contextual Info: 54LS630, SN74LS630 16 -BIT P A R A LLE L ERROR DETEC TION AN D CORRECTION CIRCUITS D 2 5 5 0 , M AR C H 1 9 8 0 -R E V IS E D M AR C H 1988 TIM 99630 • D etects and Corrects Single-Bit Errors SN 54LS630, . . . JD PACKAGE SN74LS630 . . . N PACKAGE • Detects and Flags Dual-Bit Errors

LS623

Abstract: D2537 SN74LS620
Contextual Info: S N 54LS 620, SN 54LS621, SN 74LS 620, SN 74LS 621, SM 74LS623 OCTAL BUS TRANSCEIVERS D2537, AUGUST 1979-REVISEO MARCH 1988 SN 54LS620, S N 54LS621, S N & 4 L S 6 2 2 . . . J P AC K A G E S N 74LS 620, S N 74LS621, S N 7 4 L S 6 2 3 . . . D W O R N P AC K A G E

Contextual Info: M MOTOROLA. Military 54LS645 Octal Bus Transceivers With 3-State Outputs (Non-Inverting) M m ELECTRICALLY TESTED PER: 54LS645 The 54LS645 is designed for asynchronous two-way communication between data buses. Control function implementation minimizes external

54ls645

Contextual Info: M M O T O R O L A Military 54LS645 Octal Bus Transceivers With 3-State Outputs (Non-Inverting) MPO iniin ELECTRICALLY TESTED PER: M PG 54LS645 The 54LS645 is designed for asynchronous two-way communication between data buses. Control function implementation minimizes external

Motorola ic

Abstract: 1HH1
Contextual Info: M MOTOROLA M ilita ry 5 4 L S 6 7 0 4 X 4 R eg ister File W ith 3 -S ta te O utputs E L E C T R IC A L L Y T E S T E D P ER : M IL -M -3 8 5 1 0/31901 M The 54LS670 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address

SN74LS

Abstract: SN54LS638 SN54LS639 SN74LS638 SN74LS639
Contextual Info: 54LS638, 54LS639, SM74LS638. SN74LS639 OCTAL BUS TRANSCEIVERS D2636, JANUARY 1981 -REVISED MARCH 1988 Bidirectional Bus Transceivers in HighDensity 20-Pin Packages 54LS638, SN 54LS639 . . . J PACKAGE S N 74LS638. SN 74LS 639 . . . DW OR N PACKAGE TOP VIEW

LS670

Contextual Info: LS670 a National Semiconductor 54LS670/54LS670/DM74LS670 TRI-STATE 4-by-4 Register Files General Description These register files are organized as 4 words of 4 bits each, and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data.