54LS1 Search Results

74LS169BN

Abstract: 74S169
Contextual Info: TYPES 54LS169B, SN54S168, SN54S169, SN74LS169B, SN74S168, SN74S169 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS OCTOBER 1976 —REVISED MAY 1983 S168 . . . SYNCHRONOUS UP/DOW N DECADE COUNTERS 'LS169B, 'S169 . . . SYNCHRONOUS UP/DO W N BINARY COUNTERS SN 54S 168, 5N 54LS169B, S N 54S 169 . . . J OB W PACKAGE

74LS166A

Abstract: 54ls166a 54LS166
Contextual Info: SN54166, SN 54LS166A, SN74166. SN 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS OCTOBER 1976 - REVISED MARCH 1988 S N 54166, S N 54LS 166A . . . J OR W PACKAGE S N 7416 6 . . . N PACKAGE S N 74LS 166A . . . D OR N PACKAGE • Synchronous Load • Direct Overriding Clear

IC 74LS153

Abstract: 74153 mux cd 74153 ic 74153 IC - 74LS153 74LS153 8 to 1 mux 74LS153 74153 74s153 2C011
Contextual Info: SN54153, SN 54LS153, SN 54S1S3 S N 74153, SN 74LS153, SN 74S153 DUAL 4 LINE TO 1-LINE DATA SELECTORSfM ULTIPLEXERS D E C E M B ER 1972 - R E V IS E D M A R C H 19B8 Permits Multiplexing from N lines to 1 line S N 54153, SN 5 4 LS1 5 3 , SN 5 4 S1 5 3 . . . J OR W

Contextual Info: TYPES SN54194, 54LS194A, SN54S194, SN74194, SN74LS194A, SN74S194 -BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS MARCH 1974-REVISED APRIL 1985 Parallel Inputs and Outputs SN 54194, SN 54LS194A, S N 5 4 S 1 9 4 I OR W P AC K A G E S N 7 4 1 9 4 . . . J OR N P AC K A G E

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 54LS174 DM74LS174 54LS175 54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

74LS163

Abstract: 74163 74s163 74LS163 74S163 LS163 54LS163
Contextual Info: 54/74163 4 位二进制同步计数器（同步清除） 简要说明 163 为可预置的 4 位二进制同步计数器，共有 54163/7416354S163/74S163， 54LS163/74LS163 三种线路结构形式。其主要电特性的典型值如下： 型号 fc PD

of ic 74166

Abstract: IC 74166
Contextual Info: SN54166, 54LS166A, SN74166, SN74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS O C T O B E R 197 6 - SN54166. SN 54LS166A • Sy n ch ro n o u s Load R E V IS E D M A R C H 1988 . . J OR W PACKAGE SN 74166 . . . N PACKAGE SN 74LS166A . . . D OR N PACKAGE • Direct Overriding Clear

54L157

Abstract: ic 74157 3B89 74ls158
Contextual Info: TYPES SN54157, SN54L157, 54LS157, 54LS158, SN54S157, SN54S158, SN74157, SN74LS157, SN74LS158, SN74S157, SN74S158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS M A R C H 1 9 7 4 —R E V I S E D D E C E M B E R 1983 SN 54157, SN 54LS157, SN 54S157.

SN7414

Abstract: sn7414 circuit SN414
Contextual Info: SN5414, 54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS D ECEM BER 1 9 8 3 -R E V IS E D MARCH 1988 Operation from Very Slow Edges SN&414, SN 54LS14 J OR W PACKAGE S N 7414 . . . N PACKAGE SN 74LS14 . D OR N PACKAGE • Improved Line-Receiving Characteris­

sn74155

Abstract: LS156 SN54155 SN54156 SN54LS155A SN54LS156 SN74156 SN74LS155A SN74LS156 LS155A
Contextual Info: S N 5 41 55 , S N 5 4156, S N 54LS 155A , SN 54LS156, S N 7 4 1 5 5 , S N 7 4 1 5 6 , S N 7 4 L S 1 5 5 A , S N 7 4L S 1 5 B SDLS057 DUAL 2 LINE TO 4 LINE D EC O D ER S/D E M U LTIP LE XE R S MARCH 1974 - Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demultiplexer

54175

Abstract: D313F
Contextual Info: Signetics 54175, 54LS175 Flip-Flops Quad D Flip-Flops Military Logic Products FEATURES • Four edge-triggered D flip-flops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset DESCRIPTION The 54175 and 54LS175 are quad,

770090-1

Contextual Info: M MOTOROLA Military 54LS160A Synchronous 4-Bit Decade Counter (Asynchronous Clear) M The ’LS160A is a high-speed 4-bit synchronous counter. It is edge-triggered, synchronously presettable, and cascadable MSI building blocks tor counting, memory addressing, frequency division and other

Contextual Info: TYPES SN54181, 54LS181, SN54S181, SN74181, SN74LS181, SN74S181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS DECEMBER 1972 - R E V IS E D S N 54181, SN 54LS181, SN 54S181 Full Look-Ahead fo r High-Speed Operations on Long Words DECEMBER 1983 . . . J OR W PACKAG E

Contextual Info: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE

Contextual Info: TYPES SN54H11, 54LS11, SN54S11, SN74H11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES R E V IS E D A P R IL 1 S 8 5 Dependable Texas Instruments Quality and Reliability SN54H11 . . . J PACKAGE SN 54LS11, SN 54 S1 1 . . . J OR W PACKAGE SN 74H11 . . . J OR N PACKAGE

DM74LS195AN

Abstract: DM74LS195A 54LS195A 54LS195ADMQB 54LS195AFMQB 54LS195ALMQB DM74LS195AM E20A J16A M16A
Contextual Info: 54LS195A DM74LS195A 4-Bit Parallel Access Shift Register General Description Features This 4-bit register features parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive

BCD 8421

Abstract: binary to BCD 8421 BCD 8421 application LS162 MC1455P1S synchronous counter using 4 flip flip 54LS160A 54LS160ADMQB 54LS160AFMQB 54LS160ALMQB
Contextual Info: 54LS160A DM74LS160A 54LS162A DM74LS162A Synchronous Presettable BCD Decade Counters General Description Features The ’LS160 and ’LS162 are high speed synchronous decade counters operating in the BCD 8421 sequence They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor 54LS112/54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

54LS181DMQB

Abstract: 54LS181 54LS181FMQB DM74LS181N J24A N24A W24C MAX PLUS II free alu
Contextual Info: National Semiconductor 54LS181/DM74LS181 4-Bit Arithmetic Logic Unit General Description Features The ’LS181 is a 4-bit Arithmetic Logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations.

Contextual Info: g Military 54LS173 MOTOROLA 4-Bit D-Type Register With 3-State Outputs ELECTRICALLY TESTED PER: 54LS173 M PO The 54LS173 is a high-speed 4-bit Register featuring 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing

74LS151 truth table

Abstract: DM74LS151N 74LS151 multiplexer truth table 54LS151 54LS151DMQB 54LS151FMQB 54LS151LMQB DM54LS151J DM54LS151W DM74LS151M
Contextual Info: June 1989 54LS151/54LS151/DM74LS151 Data Selector/Multiplexer General Description Features Select one-of-eight data lines Performs parallel-to-serial conversion Permits multiplexing from N lines to one line Also for use as Boolean function generator This data selector/multiplexer contains full on-chip decod­

Contextual Info: M M O T O R O L A M ilita ry 54L S 1 3 2 Quad 2-In p u t Schm itt-TVigger P ositive NAND G a te MPO mini ELECTRICALLY TESTED PER: MIL-M-38510/31303 The 54LS132 contains four 2-input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They

54LS221

Contextual Info: M M O T O R O L A M ilitary 54LS221 Dual Monostable Multivibrator, Schm itt Trigger Inputs With Enable MPO ELECTRICALLY TESTED PER: MIL-M-38510/31402 • • • /////// 54LS221 is a Dual Highly Stable One-Shot Overriding Clear Terminates Output Pulse Pin Out is Identical to 54LS123

Contextual Info: <8 > M OTOROLA SN 54LS195A SN 74LS195A D E S C R IP T IO N — T he S N 5 4 L S /7 4 L S 1 9 5 A is a h ig h speed 4 - B it S h ift R e g iste r o ffe rin g ty p ic a l s h ift fre q u e n c ie s o f 3 9 M H z. It is u s e fu l fo r a w id e v a rie ty o f re g is te r a n d c o u n tin g a p p lic a tio n s . It u tiliz e s th e