5309T Search Results
5309T Price and Stock
Microchip Technology Inc CDLL5309/TR- Tape and Reel (Alt: CDLL5309/TR) |
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CDLL5309/TR | Tape & Reel | 40 Weeks | 141 |
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CDLL5309/TR |
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CDLL5309/TR | Bulk | 500 |
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CDLL5309/TR | 40 Weeks |
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CDLL5309/TR |
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Microchip Technology Inc 1N5309/TRDiscrete Current Regulator 3mA 2.25V 2-Pin Axial DO-7 - Tape and Reel (Alt: 1N5309/TR) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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1N5309/TR | Tape & Reel | 25 Weeks | 100 |
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1N5309/TR |
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1N5309/TR | Bulk | 500 |
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1N5309/TR | 25 Weeks |
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1N5309/TR | 27 Weeks | 1 |
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1N5309/TR |
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Central Semiconductor Corp 1N5309 TR- Tape and Reel (Alt: 1N5309 TR) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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1N5309 TR | Tape & Reel | 10,000 |
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onsemi HUFA75309T3ST- Tape and Reel (Alt: HUFA75309T3ST) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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HUFA75309T3ST | Tape & Reel | 2,500 |
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Vishay Intertechnologies M39003/01-5309/TRTantalum Capacitor, 1.5 uF, 75 V, ? 5%, Axial Leaded, P, 4.7 mm, 12.04 mm - Tape and Reel (Alt: M39003/01-5309/TR) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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M39003/01-5309/TR | Tape & Reel | 36 Weeks | 1,000 |
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M39003/01-5309/TR | Tape & Reel | 1,000 |
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5309T Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: TITLE: SPECIFICATION CONTROL DRAWING PART IDENTIFIER: 5309T DESCRIPTION: HIGH POWER LOAD, BERYLLIA ASSEMBLY DWG: 1700494 1.0 SPECIFICATIONS: 1.1 ELECTRICAL: 1.1.1 RESISTANCE VALUE: 50Ω NOMINAL. 1.1.2 INPUT POWER: @ 100°C HEAT SINK, DERATED LINEARLY TO ZERO POWER AT 150°C : |
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5309t100usmil-std-130824w170+3 | |
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Contextual Info: TITLE: SPECIFICATION CONTROL DRAWING PART IDENTIFIER: 5309T DESCRIPTION: HIGH POWER LOAD, BERYLLIA ASSEMBLY DWG: 1700494 1.0 SPECIFICATIONS: 1.1 ELECTRICAL: 1.1.1 RESISTANCE VALUE: 50Ω NOMINAL. 1.1.2 INPUT POWER: @ 100°C HEAT SINK, DERATED LINEARLY TO ZERO POWER AT 150°C : |
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5309t100usmil-std-130qa0006+2 | |
FORM0357
Abstract: MIL-STD-130
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5309t100usmil-std-130qa0006+3 | |
IDT71V67703
Abstract: IDT71V67903 71V67903
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idt71v67703idt71v67903idt71v67703/7903bg119+2 | |
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Contextual Info: TERMINATIONS AND RESISTORS HIGH POWER LOADS GENERAL SPECIFICATIONS: NOTES: Power Handling: Impedance: Element: Substrate: Top Plate: • Peak power is based on 100 microsecond pulse width and 1% duty cycle. Full power at 100°C heat sink 50Q nominal Thick film, unless otherwise specified |
OCR Scan |
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IDT71V67703
Abstract: IDT71V67903 71V67903
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idt71v67703idt71v67903idt71v67703/7903119bgs+1 | |
71V67903Contextual Info: 256K X 36, 512K X 18 Advance 3.3V Synchronous SRAMs Information 3.3V I/O, Burst Counter IDT71V67703 Flow-Through Outputs, Single Cycle Deselect IDT71V67903 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ data, address and control registers. There are no registers in the data |
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idt71v67703idt71v67903117mhz100mhz+6 | |
IDT71V67703
Abstract: IDT71V67903 71V67903
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idt71v67703idt71v67903idt71v67703/7903119bgs+1 | |
5309LContextual Info: HIGH POWER LOADS GENERAL SPECIFICATIONS: NOTES: Power Handling: Impedance: Element: Substrate: Top Plate: • Peak power is based on 100 microsecond pulse width and 1% duty cycle. Full power at 100°C heat sink 50Q nominal Thick film, unless otherwise specified |
OCR Scan |
5309l | |
71V67903Contextual Info: 256K X 36, 512K X 18 IDT71V67703 3.3V Synchronous SRAMs IDT71V67903 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ data, address and control registers. There are no registers in the data output path flow-through architecture . Internal logic allows the SRAM to |
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idt71v67703idt71v67903idt71v67703/7903bq165+3 | |
IDT71V67703
Abstract: IDT71V67903 71V67903
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idt71v67703idt71v67903idt71v67703/7903bq165+3 | |
71V67903Contextual Info: 256K X 36, 512K X 18 IDT71V67703 3.3V Synchronous SRAMs IDT71V67903 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ data, address and control registers. There are no registers in the data output path flow-through architecture . Internal logic allows the SRAM to |
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idt71v67703idt71v67903117mhz100mhz+6 |