4BBFI03 Search Results

qs52805atq

Abstract: ob3 diode
Contextual Info: ADVANCED INFORMATION QS5805T/AT, QS52805T/AT QS5806T/AT, QS52806T/AT Guaranteed Low Skew CMOS Clock Driver/Buffer FEATURES • 10 output, low skew clock signal buffer • 25 Q on-chip resistors available for low noise • Reduced swing TTL outputs for low noise

QS3J245

Contextual Info: QS3J245 ADVANCE INFORMATION QuickScan 8-Bit Universal JTAG Access Port with Output Enable QS3J245 FEATURES/BENEFITS • • • • • • IEEE 1149.1 - 1993 compliant Direct bus connection when switches on Superset pinout of a '245 Undershoot clamp diodes on all inputs

Contextual Info: QS72211, QS72221, QS72231, QS72241 PRELIMINARY High-Speed CMOS 512/1K/2K/4K x 9 Parallel Clocked FIFO Q QS72211 QS72241 FEATURES DESCRIPTION • 5 1 2 x 9 QS72211 • 1K X 9 (QS72221) 2K x 9 (QS72231) • 4K x 9 (QS72241) • Ultra-high speed 12-ns (83 MHz)

Contextual Info: QS72231, QS72241 ADVANCE INFORMATION Q High-Speed CMOS 2K x 9, 4K x 9 Parallel Clocked FIFO QS72231 QS72241 FEATURES • • • • 15-ns 66-MHz read/write cycle times Synchronous/asynchronous read and write TTL input and output level compatible Low power with industry-standard pinouts

Contextual Info: QS74FCT16374T, QS74FCT162374T ADVANCE INFORMATION Q High Speed CMOS 16-Bit Registers 3-State QS74FCT16374T qs74fcti623?4t FEATURES/BENEFITS Pin and function compatible with T.l. Widebus and IDT Double-Density™ families CMOS power levels: <1 nW typical standby

Contextual Info: QS723651. QS723661 PRELIMINARY High-Speed CMOS 2K x 36, 4K x 36 Clocked FIFO Q QS723651 QS723661 FEATURES • • • • • • Clocked interface 2K/4K x 36 FIFO Programmable Almost-Full and Empty flags Bi-directional mailbox registers Adjustable retransmit

ITT taa 775

Abstract: 014L transistor CASE DIODE A5L QS702 a6l diode
Contextual Info: QS7025A PRELIMINARY High-Speed CMOS 8 K X 1 6 QS7025A Asynchronous Dual-Port RAM FEATURES/BENEFITS • High-speed asynchronous dual-port architecture • Independent port access and control • Access times from either port, 25/35/45/55 ns • Master/slave pin, for width expansion

QS5244T

Contextual Info: QS5244T High Speed CMOS 8-Bit Buffers/Line Driver Ô QS5244T FEATURES/BENEFITS • » • • • 0.5 ns on-chip skew same transition 244 compatible pinout and function Ground bounce controlled outputs TTL voltage swing of 0-3.5V 4.1 ns propagation delay

431h

Contextual Info: QS74FCT2X377T PRELIMINARY Q High Speed CMOS 16-Bit Register with Clock Enable in QVSOP QS74FCT2X377T FEATURES/BENEFITS • Function compatible to the 74F377 74FCT377 and 74ABT377 • CMOS power levels: <15 mW static • Undershoot clamp diodes on all inputs

823T

Abstract: 2823a 825T
Contextual Info: QSFCT821T, 823T, 825T, 2821T, 2823T, 2825T QS54/74FCT821T QS54/74FCT823T QS54/74FCT825T High Speed CMOS Bus Interface 8-, 9-, and 10-Bit Registers Q QS54/74FCT2821T QS54/74FCT2823T QS54/74FCT2825T FEATURES/BENEFITS • Pin and function compatible to the 74F821/3/5

D23R

Abstract: D2L DIODE D17R diode d5r d25r 74FCI D26R 74*b03
Contextual Info: QS75436 ADVANCE INFORMATION Q High-Speed CMOS 4K x 36 Block-Allocated Shared-Port RAM with Flexi-Burst 6 FEATURES • Two independent 2K x 36-bit blocks • Independent port controls • Fast port access times: 20 ns, 25 ns, 30 ns - 50-MHz, 40-MHz, 33-MHz cycle times

Contextual Info: QS6612 Preliminary Data Sheet Rev. 2.4 QS6612 lO/lOOBaseTX M il Transceiver for Category 5 Twisted Pair Cable Ô 1.0 QS6612 DISTINCTIVE FEATURES IEEE 802.3u compliant M il and Serial Management standard interface IEEE 802.3u compliant Auto-Negotiation for auto

LZ 173 relay

Contextual Info: QS6810 PRELIMINARY Q 4:1 ATM MuIti plexer/Dem uIti plexer QS6810 FEATURES Full-duplex 4:1 ATM cell mux/demux High speed, up to 800-Mb/s transfer rate 18-Kbit FIFO buffering on chip Expandable up to 30-to-1 mux/demux Variable cell length for routing tag insertion

Contextual Info: QS72215, QS72225 Ô High-Speed CMOS 512 x 1 8 ,1K x 18 Parallel Clocked FIFO QS72215 QS72225 FEATURES • CMOS dual-port SRAM technology, 512 x 18 or 10 24x 18 • Fast cycle times: 20/25/35 ns • Choice of standard or enhanced operating mode • Device comes up into one of two known default