7MBBFL03 Search Results

P 32240

Contextual Info: QSFCT3240, 3244, 32240, 32244 PRELIMINARY 3.3 Volt CMOS 8-BÌt Q QS74FCT3240 QS74FCT3244 Buffers/Line Drivers JgÏ Ï S S J Î FEATURES/BENEFITS • • • • • Pin and function compatible to the 74F240/4 74LVT240/4 and 74FCT240T/4T Available in SOIC and QSOP

Contextual Info: QS723620 Ô High-Speed CMOS 1 K X 3 6 Clocked FIFO with Bus Sizing QS723620 FEATURES • Fast cycle times: 20/25/30 ns • Selectable 36/18/9-bit word width for both input port and output port • Byte-order-reversal function i.e., “big-endian” o “little-endian” conversion

Contextual Info: Q u a lity Sem iconductor, Inc. 3.3V Programmable Skew qssv993 PLL Clock Driver m p r e l im in a r y T u r b O u lO C k FEATURES/BENEFITS DESCRIPTION • The QS5V99X family is a high fanout 3.3V PLL based clock driver intended for high performance computing

8-QSOP

Contextual Info: 2UALITY S E M I C O N D U C T O R INC M1E D • 74bbfl03 G 0 G G 5 b 2 Q ■ Ö S I (p ~ ^ QSFCT29520T, 29521T, 252ÖT, 2521T Q High Speed CMOS ■ r i Multilevel Pipeline Registers SSJSESi*?!! QS29FCT521T qs2 9 fc t 252 ot Q S29FCT2521T FEATURES/BENEFITS

QS32XL384

Contextual Info: QS32XL384 High-Speed CMOS 20-Bit Bus Switches in QVSOP Q QS32XL384 FEATURES/BENEFITS Low power 6 |iA Icc Four enables control five bits each Zero ground bounce in flow-through mode TTL-compatible input and output levels • 5Q switches connect inputs to outputs

Contextual Info: QS74FCT16652T, QS74FCT162652T PRELIMINARY High Speed CMOS 16-Bit Bit Bus Register Regis Transceiver ô QS74FCT162652T FEATURES/BENEFITS • Pin and function compatible with T.l. Widebus and IDT Double-Density™ families • CMOS power levels: <1 n.W typical standby

Contextual Info: ÛUALITY SEMICO NDU CTOR INC bSE D QSFCT861 /2/3/4T, • 74bbñQ3 00D13BG HÛ7 * 0 S I 2861/2/3/4T Q S 54/74FC T861T Q S 54/74FC T862T Q S 54/74FC T863T Q S 54/74FC T864T High Speed CMOS Bus Interface 9 & 10-bit Transceivers Q Q S 54/74F C T2861T Q S54/74FC T2862T

Contextual Info: ÛUALITY SEMICONDUCTOR INC bSE D B 74bbfl03 G D D H b 2 D7H QSFCT161T, 2161T, 163T, 2163T Q High-Speed CMOS Synchronous Presettable 4-Bit Binary Counters QS54/74FCT161T QS54/74FCT163T QS54/74FCT2161T Q S54/74FCT2163T FEATURES/BENEFITS • Pin and function compatible to the 74F161/3

Contextual Info: QS72211, QS72221 ADVANCE INFORMATION Q High-Speed CMOS 512X 9, 1K X 9 QS72221 Parallel Clocked FIFO FEATURES • • • • 15-ns 66 MHz read/write cycle times Synchronous/asynchronous read and write TTL compatible input and output levels Low power with industry-standard pinouts

Contextual Info: QS4A215Q1 PRELIMINARY High-Performance CMOS Analog 6-Bit 4:1 Mux/Demux Q FEATURES QS4A215Q1 GENERAL DESCRIPTION Low on-resistance: rDs on = 5Q Fast transition time: tjRAN = 6 ns W ide bandwidth: 700 MHz (-3 dB point) Crosstalk: -1 1 0 dB @ 50 KHz, -6 6 d B @ 30 MHz

Contextual Info: QS3125 PRELIMINARY High-Speed CMOS Quadruple Bus Switches with Individual Enables FEATURES/BENEFITS • • • • Switches connect inputs to outputs Direct bus connection when switches are ON Pin compatible with the 74'125 function Available in SOIC S1 , QSOP

D3254

Contextual Info: QS7024A PRELIMINARY High-Speed CMOS 4K x 16 Asynchronous Dual-Port RAM Q FEATURES QS7024A DESCRIPTION High-speed asynchronous dual-port architecture Access times from either port, 20/25/35/55 ns Industry standard pin-out Independent port access and control

Contextual Info: ÖUALITY SEM ICO NDUCTOR INC MIE D • 74bbfl03 GD0Q477 H H Ö S I T -H 6 -3 r QS7203, QS72Ö4 Q 2Kx9: QS7203 4Kx9: QS7204 PRELIMINARY High Speed CMOS 9-bit FIFO Buffer Memories FEATURES/BENEFITS • • • • • • 15 ns flag and data access times ' Fully Asynchronous Read and Write

Contextual Info: QS74FCT4X373T, QS74FCT4X2373T High Speed CMOS "L. 32-Blt Latch in MillipaQ Ö QS74FCT4X373ATQ3 QS74FCT4X373CTQ3 QS74FCT4X2373ATQ3 FEATURES/BENEFITS DESCRIPTION • 32-bit Function compatible to the 74F373 74ABT373, 74FCT373T and 74FCT2373T • QS74FCT4X373T: Iol = 48 mA

Contextual Info: QS72231, QS72241 ADVANCE INFORMATION Q High-Speed CMOS 2K x 9, 4K x 9 Parallel Clocked FIFO QS72231 QS72241 FEATURES • • • • 15-ns 66-MHz read/write cycle times Synchronous/asynchronous read and write TTL input and output level compatible Low power with industry-standard pinouts

Contextual Info: QSFCT3540, 3541, 32540, 32541 PRELIMINARY Q 3.3 Volt CMOS QS74FCT3540 QS74FCT3541 g g jj Buffers/Line Drivers qs74fct3254i FEATURES/BENEFITS • • • • • Pin and function compatible to the 74F540/1 74LVT540/1 and 74FCT540T/1T Available in SOIC and QSOP

Contextual Info: QS74FCT16374T, QS74FCT162374T ADVANCE INFORMATION Q High Speed CMOS 16-Bit Registers 3-State QS74FCT16374T qs74fcti623?4t FEATURES/BENEFITS Pin and function compatible with T.l. Widebus and IDT Double-Density™ families CMOS power levels: <1 nW typical standby

Contextual Info: ÛUALITY SEMI CONDUCTOR INC bSE D Q S7203, • ?Mbbô03 DDQlDUb T4Ü H Û S I QS7204 High Speed CMOS 9-bit FIFO Buffer Memories Q 2Kx9: QS7203 4Kx9: QS7204 F E A T U R E S / B E N E F IT S • 10 ns flag and data access times • Fully Asynchronous Read and Write

74F257

Abstract: QS32257 74FCT257T 74FCT257
Contextual Info: QS32257 ADVANCE INFORMATION High-Speed CMOS QuiCkSwitCh Quad 2:1 Mux/Demux with Series Resistors QS32257 FEATURES/BENEFITS • • Low on resistance switches connect inputs to outputs Pin compatible with the 74F257, 74FCT257, and 74FCT257T • Low power CMOS technology

QS72211

Contextual Info: QS72211, QS72221 ADVANCE INFORMATION Q High-Speed CMOS 5 1 2 x 9 , 1K X 9 Parallel Clocked FIFO QS72211 QS72221 FEATURES • • • • 15-ns 66 MHz read/write cycle times Synchronous/asynchronous read and write TTL compatible input and output levels Low power with industry-standard pinouts

Contextual Info: QS6612 Preliminary Data Sheet Rev. 2.4 QS6612 lO/lOOBaseTX M il Transceiver for Category 5 Twisted Pair Cable Ô 1.0 QS6612 DISTINCTIVE FEATURES IEEE 802.3u compliant M il and Serial Management standard interface IEEE 802.3u compliant Auto-Negotiation for auto

Contextual Info: QS70681 PRELIMINARY Q High-Speed CMOS 16K x 18 Asynchronous Dual-Port RAM QS70681 FEATURES/BENEFITS • • • • • • • High-speed asynchronous x18 dual-port RAM architecture Independent port access and control Access times from either port, 25/35/45/55 ns

LZ 173 relay

Contextual Info: QS6810 PRELIMINARY Q 4:1 ATM MuIti plexer/Dem uIti plexer QS6810 FEATURES Full-duplex 4:1 ATM cell mux/demux High speed, up to 800-Mb/s transfer rate 18-Kbit FIFO buffering on chip Expandable up to 30-to-1 mux/demux Variable cell length for routing tag insertion

Contextual Info: Guaranteed Low Skew CMOS s e m Z u c to r .In c . Clock Driver/puffer q ssso s , q s 5806 QS52805, QS52806 in f o ardmvA t io n FEATURES/BENEFITS DESCRIPTION • • • • • • The QS5805 and QS5806 clock driver/buffer circuits can be used for clock buffering schemes where low