4A2L17S Search Results

Contextual Info: intJ. 2-MBIT 128K x 16, 256K x 8 LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B m Low Voltage Operation for Very Low Power Portable Applications — Vcc = 3.0V-3.6 V • Automatic Power Savings Feature — 0.8 mA Typical Ice Active Current in

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

Contextual Info: Ä P M Ä IM ! OM F©KffiíL&YO©M in te i 82374EB/82374SB EISA SYSTEM COMPONENT (ESC In te g ra te s E ISA C o m p a tib le Bus C o n tro lle r — T ra n s la te s C y cles B e tw e e n E ISA and ISA Bus — S u p p o rts E IS A B u rst an d S tan d ard

Contextual Info: Ä E W M O i O M IP O ^ ß M Ü ’O !?!!] 82375EB/82375SB PCI-EISA BRIDGE PCEB • Provides the Bridge Between the PCI Local Bus and EISA Bus ■ 100% PCI and EISA Compatible — PCI and EISA M aster/S lave Interface — Directly Drives 10 PCI Loads and 8

Contextual Info: P fö H y K ä M Ä G W in te i 80L960JA/JF 3.3V EMBEDDED 32-BIT MICROPROCESSOR 3.3 V Version o f the 80960JA/JF Processor Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model

fA80486SX

Contextual Info: in te i EMBEDDED ULTRA-LOW POWER Intel486 SX PROCESSOR Ultra-Low Power Version of the Intel486 SX Processor — 32-Bit RISC Technology Core — 8-Kbyte Write-Through Cache — Four Internal Write Buffers — Burst Bus Cycles — Dynamic Bus Sizing for 8- and 16-bit

8XC196KC instruction set

Contextual Info: in te i A28F200BX-T/B 2-MBIT 128K x 16, 256K x 8 BOOT BLOCK FLASH MEMORY FAMILY Automotive x8/x16 Input/Output Architecture — A28F200BX-T, A28F200BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs Optimized High Density Blocked Architecture

Contextual Info: in te i SPECIAL ENVIRONMENTS PENTIUM PROCESSOR at iCOMP® INDEX 815X100 MHz AND 1000X120 MHz Compatible with Large Software Base -M S -D O S *, Windows*, OS/2*, UNIX* 32-Bit CPU with 64-Bit Data Bus Multi-Processor Support — Multiprocessor Instructions

Contextual Info: O M [P § » Ä Y O M in te i 80960HA/HD/HT 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR 3.3V Supply Voltage — 5V Tolerant Inputs — TTL Compatible Outputs 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers

82420EX

Contextual Info: in te i 82420EX PCISET DATA SHEET 82425EX PCI SYSTEM CONTROLLER PSC AND 82426EX ISA BRIDGE (IB) Host CPU - 2 5 - 3 3 MHz ln te l4 8 6 T M and Programmable Attribute Map for First 1 MByte of Main Memory O v e rD riv e P ro ce ss o rs 100% ISA Compatible

GIGABYTE G41

Abstract: 82360SL intel 82360SL
Contextual Info: INTEL CORP UP/PRPHLS 3IE D 402tl7S 00aSbb7 2 int@l 7 = V f-/7 -^ 2 386TM SL MICROPROCESSOR SuperSet Highly-Integrated Static 386 Microprocessor Complete ISA Peripheral Subsystem System-Wide Power Management Static 386™ CPU Core — Runs MS-DOS*, WINDOWS*, O S/2*

Contextual Info: 80C196KB10/83C196KB10/80C196KB12/83C196KB12 PACKAGING The 80C196KB is available in a 68-pin PLCC package, an 80-pin QFP package and a 68-pin PGA package. Contact your local sales office to determine the exact ordering code for the part desired. Package Designators: N = 68-pin PLCC, S = 80-pin QFP and A = 68-pin PGA.

transistor bl p81

Abstract: transistor bl p87
Contextual Info: [p[F3 [0> !J T [PIFSEVOE^ in y 83C196EA CHMOS 16-BIT MICROCONTROLLER Automotive 32 MHz operation Optional clock doubler 2 Mbytes of linear address space 1 Kbyte of register RAM 3 Kbytes of code RAM 8 Kbytes of ROM Register-to-register architecture Stack overflow/underflow monitor with

Contextual Info: in y CHAPTER 6 INSTRUCTION SET REFERENCE This chapter provides detailed information about each instruction available to the i960 Jx processors. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in section 6.1, “NOTATION” pg. 6-1 .

TDA 11136 PS

Abstract: tda 11135
Contextual Info: AGWAKKSS 0 MF [F3G!MYO®(i! MILITARY ¡386 SX MICROPROCESSOR • Full 32-Bit Internal Architecture - 8 - , 16-, 32-Bit Data Types — 8 General Purpose 32-Bit Registers ■ Virtual M8086 Mode Allows Execution of M8086 Software in a Protected and Paged System

Contextual Info: P R IS IL D B m A lffir i n t e i 8XC52/54/58 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C52/80C52/80C32/87C54/80C54/87C58/80C58 •S e e Table 1 for Proliferation Options High Performance CHMOS EPROM/ ROM/CPU 6 Interrupt Sources Programmable Serial Channel with:

Contextual Info: in te i 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Perform s Com plete C SM A/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting High-Performance 16-/32-B it Bus

82077sl

Abstract: SK 6211 intel floppy disk controller 8272 82072 FDC 82077SL
Contextual Info: in te i 82077AA CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER Single-Chip Floppy Disk Solution — 100% PC AT* Compatible — 100% PS/2* Compatible — 100% PS/2 Model 30 Compatible — Integrated Drive and Data Bus Buffers Integrated Tape Drive Support 12 mA Host Interface Drivers, 40 mA

scr tic 1160

Abstract: Cote Micro Technique 01BS2
Contextual Info: in t é l 82596DX AND 82596SX HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting Supports Industry Standard LANs — IEEE TYPE 10BASE-T (TPE),

M771

Contextual Info: in te i 82C37A-5 CHMOS HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER Pin Compatible with NMOS 8237A-5 • Address Increment or Decrement Enable/Disable Control of Individual DMA Requests ■ High performance: 5 MHz Speed Transfers up to 1.6 MBytes/Second Fully Static Design with Frequency

I80186

Abstract: ARCHITECTURE OF 80186 PROCESSOR d1435 opcode sheet for 8086 microprocessor 80186 a13837 LTMV intel DMA controller Unit for 80186 80C186XL 80188 programming
Contextual Info: in t e i, 80186/80188 HIGH-INTEGRATION 16-BIT MICROPROCESSORS Integrated Feature Set — Enhanced 8086-2 CPU — Clock Generator — 2 Independent DMA Channels — Programmable Interrupt Controller — 3 Programmable 16-bit Timers — Programmable Memory and

82C54-2

Abstract: 82C54 microprocessors interface 8086 to 8253 8254 aa intel DOC 8253 programmable interval timer C882C54
Contextual Info: in tj 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER Compatible with all Intel and most other microprocessors High Speed, “Zero Wait State” Operation with 8 MHz 8086/88 and 80186/188 Handles inputs from DC — 10 MHz for 82C54-2 • Three independent 16-bit counters

P28F001

Abstract: 28F001BX-B 28F001BXB
Contextual Info: in te i • 1-MBIT 128K x 8 BOOT BLOCK FLASH MEMORY 28 F 0 0 1 B X - T /2 8 F 0 0 1 B X -B /2 8 F 0 0 1 B N - T /2 8 F 0 0 1 B N -B u High-Integration Blocked Architecture — One 8 KB Boot Block w/Lock Out — Two 4 KB Parameter Blocks — One 112 KB Main Block