4821 Search Results

14851

Abstract: CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 IDT72801 IDT728X1 DA6116
Contextual Info: fax id: 5414 CY7C4801/4811/4821 CY7C4831 /4841 /4851 256/512/1 K/2K/4K/8K x9 x2 Double Sync FIFOs Features • Double high speed, low power, first-in first-out FIFO memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double 1 K x 9 (4821)

1010 817 g40

Abstract: GT-64111 I960JX
Contextual Info: GT-482xx liiii d | | |G O . GT-48212 / GT-48208 / GT-48207 Prelim inary Revision 1.2 D v 1/27/99 BaseX Please co n ta ct G alileo T echnology fo r possible u p dates b efore fin a lizin g a design. FEATURES • - - • - Provides packet switching functions between

60PEN

Abstract: Amphenol Pcd
Contextual Info: REV ELFH SERIES ELF PART N UMBERIN G SCHEME H TYPE HEADER OPTIONS NUMBER OF POSITIONS — COLOR/PLATING R /A , VERTICAL: 0 2 - 2 4 0=BLACK, TIN (STANDARD) MOUNTING EARS: 0 2 - 2 2 1=BLACK, SELECTIVE GOLD ECN 3730 3865 3899 4295 4711 4821 5071 5178 5742 APPD

GT-48212

Abstract: TC3001 IC TC3001 "filtering database" GT-48208 GT-64010A GT-64120 Motorola ColdFire 5202 led matrix 16X32 intel 80486 pin diagram
Contextual Info: GT-48212 Advanced Switched Fast Ethernet Controller for 10+10/100 BaseX Preliminary Revision 1.0 March 4, 1998 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • Single-chip Switched Ethernet Controller for 10 and

Contextual Info: fax id: 5414 CY7C4801/4811/4821 CY7C4831 /4841 /4851 256/512/1 K/2K/4K/8K x9 x2 Double Sync FIFOs Featu res Double high speed, low power, first-in first-out FIFO memories Double 256 x 9 (CY7C4801) Double 512 x 9 (CY7C4811) Double 1 K x 9 (4821) Double 2K x 9 (CY7C4831)

AC DC pwm controller rectifier

Abstract: cpu intel 8085 pin diagram of Dual core cpu IRF7811W MPC1055LR36 NTCG163JH103F Si4386DY Si4642DY NTC 10k thermal sensor
Contextual Info: 19-4821; Rev 0; 7/09 Dual-Phase, Quick-PWM Controller for IMVP-6.5 CPU Core Power Supplies LX2 DH2 PGND2 DL2 VRHOT VDD DL1 PGND1 IMVP-6.5 Core Supply LX1 TOP VIEW BST1 Applications Pin Configuration DH1 The MAX17582 is a 2-/1-phase-interleaved QuickPWM step-down VID power-supply controller for

2TW/170

Contextual Info: REV ELFP SERIES PART NUMBERING SCHEME - A B C D E ELE P TYPE RIGHT ANGLE - ECN 3600 3865 4686 4761 4821 5742 APPD JEC 12/11/98 JEC 11/9/99 IQ 1/2/02 IQ 2/20/02 IQ 4/4/02 )2tW i2T2fi/cr OPTIONS COLOR/PLATING NUMBER OF POSITIONS — 0=BLACK, TIN (STANDARD)

"Digital Delay Line"

Abstract: AD9288 ISL5740
Contextual Info: ISL5740 TM Data Sheet P RE L I M I NA R Y June 2000 File Number 4821.2 3V Dual 10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference Features The ISL5740 is a monolithic, dual 10-bit analog-to-digital converter fabricated in an advanced CMOS process. It is

Contextual Info: MCP4801/4811/4821 8/10/12-Bit Voltage Output Digital-to-Analog Converter with Internal VREF and SPI Interface Features Description • • • • • • The MCP4801/4811/4821 devices are single channel 8-bit, 10-bit and 12-bit buffered voltage output Digital-to-Analog Converters DACs , respectively. The

Contextual Info: fax id: 5414 CY7C4801/4811/4821 CY7C4831/4841/4851 CYPRESS 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs Features • Double high speed, low power, first-in first-out FIFO memories • Double 256 x 9 (CY7C4S01) • Double 512 x 9 (CY7C4811) • Double 1K x 9 (4821)

Contextual Info: P ulse/Tone D ialer LSI 48211 • 48211 Pulse/Tone Dialer LSI Pin Connections Description The L R 48211 is a CMOS pulse/tone dialer LSI providing auto-dialing and redialing. It features a built-in 16-digit X 15-channel automatic dialing mem­ ory including a 16-digit X 5 one-touch memory, a 16digit X 10 tw o-touch m em ory and a 32-digit redial

"filtering database"

Abstract: DP8384Q I960CX IC TC3001 "Spanning Tree" BUT15
Contextual Info: Galileo. GT-48212 Advanced Switched Fast Ethernet Controller for 10+10/100 BaseX Please contact Galileo Technology for possible updates before finalizing a design FEATURES • Single-chip Switched Ethernet Controller for 10 and 1CV100Base-X - Provides packet switching functions between

4036

Abstract: 2SA1812 1.4934 BY 143
Contextual Info: SPICE PARAMETER 2SA1812 by ROHM TR Div. * Q2SA1812 PNP BJT model * Date: 2006/12/18 .MODEL Q2SA1812 PNP + IS=550.00E-15 + BF=118.60 + VAF=24.033 + IKF=.4821 + ISE=550.00E-15 + NE=1.4036 + BR=4.8184 + VAR=100 + IKR=1.4934 + ISC=506.15E-12 + NC=1.5119 + NK=.89675

4821

Abstract: aos Lot Code Week A04821 PD0034
Contextual Info: Document No. ALPHA & OMEGA SEMICONDUCTOR Version Title SO-8 PACKAGE MARKING DESCRIPTION LOGO 4 8 2 1 F A Y W LT O Green product NOTE: LOGO 4821 F&A Y W LT - AOS LOGO - PART NUMBER CODE. - FOUNDRY AND ASSEMBLY LOCATION - YEAR CODE - WEEK CODE. - ASSEMBLY LOT CODE

Contextual Info: 48212 Data Sheet May 1999 Digital Video Mixer Features The Harris H S P 48212 is a 68 pin Digital Video M ixer IC • 12-B it Pixel D ata intended for use in m ultim edia and m edical im aging File Number 3627.2 • Two’s C o m p le m e n t o r U nsigned Data

4M64

Abstract: "Spanning Tree" BUT15
Contextual Info: Galaxy Family Devices lia lile o G T-48212 / G T-48208 / GT-48207 Advanced Switched Ethernet Controllersfor 10+10/100 BaseX for 10OBaseX Please contact Galileo Technology for possible updates before finalizing a design FEATURES • Single-chip Switched Ethernet Controllers for 10 and

CY7C4801

Abstract: CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851
Contextual Info: CY7C4831/4 1 CY7C4801/4811/4821 CY7C4831/4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs Features • Double high speed, low power, first-in first-out FIFO memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double 1K x 9 (4821)

AD9288

Abstract: HI574 60MS
Contextual Info: Data Sheet P RE L I M I NA R Y December 1999 File Number 4821 3V Dual 10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference Features The HI5740 is a monolithic, dual 10-bit analog-to-digital converter fabricated in an advanced CMOS process. It is

Contextual Info: CAMBION Wearnes Cambion LTD â Castleton, Hope Valley, Derbyshire, S33 8WR, England Telephone: +44 0 1433 621555 Fax: +44(0)1433 621290 Web: www.cambion.com Email: enquiries@cambion.com Technical Data Sheet 572-4821, Insulated solder terminal, turret type

CY7C4831

Abstract: CY7C4841 CY7C4851 CY7C4801 CY7C4811 CY7C4821
Contextual Info: CY7C4831/4 1 CY7C4801/4811/4821 CY7C4831/4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs Features • Double high speed, low power, first-in first-out FIFO memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double 1K x 9 (4821)

marking code cl

Contextual Info: REV ELFF SERIES PART NUMBERIN G SCHEME ELF F TYPE FRONT WIRE E N T R Y / FRONT ACTUATION J ECN APPD 3600 4686 47 9 2 4821 574 2 JC 1 2 /1 1 /9 8 IQ 1 / 2 / 0 2 IQ 3 /1 1 / 0 2 IQ 4 / 9 / 0 2 OPTIONS COLOR/PLATING NUMBER OF POSITIONS — 0=BLACK, TIN (STANDARD)

AD9288

Abstract: ISL5740 Analog Devices Pin Compatible Upgrade for
Contextual Info: ISL5740 TM Data Sheet P RE L I M I NA R Y June 2000 File Number 4821.2 3V Dual 10-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference Features The ISL5740 is a monolithic, dual 10-bit analog-to-digital converter fabricated in an advanced CMOS process. It is

2SA1727

Contextual Info: SPICE PARAMETER 2SA1727 by ROHM TR Div. * Q2SA1727 PNP BJT model * Date: 2006/12/18 .MODEL Q2SA1727 PNP + IS=550.00E-15 + BF=118.60 + VAF=24.033 + IKF=.4821 + ISE=550.00E-15 + NE=1.4036 + BR=4.8184 + VAR=100 + IKR=1.4934 + ISC=506.15E-12 + NC=1.5119 + NK=.89675

C483

Abstract: CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851
Contextual Info: fax id: 5414 1Do uble CY7 C483 1/ 4 84 1/4 85 1 CY7C4801/4811/4821 CY7C4831/4841/4851 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs Features • Double high speed, low power, first-in first-out FIFO memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811)