44TBE Search Results

Contextual Info: H IT A C H I/ L O G I C / A R R A Y S /flEd ^2 D E I 44TbE03 D D lD t4 2 92D HD74HCT238 • fi 10642 3-to-8-line Decoder/D em ultiplexer The HD74HCT238 has 3 binary select inputs A, B, and C . if the device is enabled these inputs determined which one of

BL 3030L

Contextual Info: fc>lE J> m 44TbED3 D D E l i n E3E • H I T E HM621400 Series- Preliminary 4194304-word x 1-bit High Speed CMOS Static RAM The Hitachi HM621400 is a high speed CMOS static RAM organized 4 Mword x lbit. It realizes higher performance and low power consumption

2SK1763

Abstract: 44TB2 Hitachi Scans-001
Contextual Info: blE ]> • 44TbEG5 ÜQlBSEb fl47 « H I T 4 2SK1763 , 2SK1763 s Silicon N Channel MOS FET HITACHI/(OPTOELECTRONICS) Application High speed power switching Features • • • • Low on-resistance High speed switching Low drive current 4 V gate drive device — can be driven from

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM ^2 HD74HC242 HD74HC243 92D 10459 # Quad. Bus Transceivers with 3-state outputs # Quad. Bus Transceivers The HD74HC242 is an inverting bu ffer and the HD74HC243 is a noninverting buffer. DEI 44TbEQ3 OOlOMST b~|~ enable (G BA), and one active low enable (GAB).

zener diode si 18

Abstract: 1N763 1N764 1N765 1N762 1N767 1N768 1n76 1N761 1N766
Contextual Info: 4496205 H 1 IACHÌ / <OPTOtCÈCtRONìCS 37C 0 2 2 2 3 37 4 0 0 m U U 1 N 7 6 1 Z e n e r th r u d T -//« n ? — — D eT | 44TbEDS 0002523 D i o co / ee s •> r 1 N 7 6 9 G€N€AAl D6SCRIPTION The Hitachi 400mW ZENER DIODE series 1N761 THRU 1N769 are especially designed for stabilized power

2SK1763

Contextual Info: blE ]> • 44TbEG5 ÜQlBSEb fl47 « H I T 4 2SK1763 , 2SK1763 s Silicon N Channel MOS FET H I T A C H I / (OPTOELECTRONICS) Application High speed power switching Features • • • • Low on-resistance High speed switching Low drive current 4 V gate drive device — can be driven from

hitachi hmcs

Contextual Info: HITACHI/ tlCU/MPU 1ÔE D 44TbE04 0017GÔ7 G I H M C S 4 2 4 C /H M C S 4 2 4 C L/ H M CS424AC t ^ . oh H D404240/H D40L4240/H D40A4240 Description • The HMCS424C/CL/AC aie GMOS 4-bit single-chip microcomputers in th e HMCS400 series. Each device incorporates ROM, RAM,

2SK619

Abstract: J10V diode gate
Contextual Info: 2SK 619 blE D 44TbE0S 0013103 bib • HITH HITACHI/ OPTOELECTRONICS SILICON N-CHANNEL MOS FET it rT HIGH FREQUENCY HIGH IMPEDANCE AMPLIFIER ì h ■ FEATURES • • High Voltage (VDSS - 70 V) Effective to Suppress Signal Radiation Connected Source to Heat Sink

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM Ì2 dÊ J 44^303 0D1D44L. A | - HD74HC195 92D 10446 # 4-bit Parallel-Access Shift Register This shift register feetures parallel inputs, parallel outputs, J-K serial inputs, S hift/L oad control input, and a direct | D T- Hb -O l-ß S

Contextual Info: H I T A C H I / LOGIC/ARRAYS/flEH ^5 4 4 ^ 5 0 3 0010b44 1 92D HD 74H C T240 # 10644 D ]~'SZ-<>7 Octal B u ffers/Line D rivers/L ine Receivers with inverted 3-state outputs PIN ARRANGEMENT The HD74HCT240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently con­

Contextual Info: Ï Ë J 4 4 cit,2D3 G G 1 D 3 S 7 1 J H I T A C H I / L O G I C / A R R A Y S / N E M "il 92D HD74HC91 üT-ïé-ûf-O 10357 • 8 - bit Shift Register This serial-in, serial-out, 8-bit shift register is composed o f eight R-S master-slave flip-flo ps, inpu t gating, and a clock

Contextual Info: HITACHI/ LOGIC/ARRAYS/HEfl TS D E | l44^13203 D O l O M h T ; HD74HC257 92D T 10469 D # Quad.2-to- 1-line Data Selectors/Multiplexers with noninverted 3-state outputs) -T -lcH-'LlSl PIN ARRANGEMENT The large output drive capability coupled with the 3-state

Contextual Info: HITACHI/ L O G IC /A RRAYS/ NEN ^2 D E I 4 4 ^ 5 0 3 GD1D413 4 J ~ 92D HD74HC165 # 10413 Parallel-load 8-bit Shift Register This 8-bit serial shift register shifts data fro m Q A to Q h T-46-09-05 PIN ARRANGEMENT when clocked. Parallel inputs to each stage are enabled by a

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEN T2 DEI 4 4IikiE03 0010404 S > HD74HC298 92D 10484 # Quad. 2-input Multiplexers with storage) PIN ARRANGEMENT This circuit is controlled by the signals word select and clock. When the word select input is taken low w ord 1 (A 1, B i,

Contextual Info: HITACHI/ L O G I C / A RR AYS/ HE M TE HD74HC620 HD74HC623 % D E | 44Tt>203 0Q1QSS7 t> 92D 10557 o T 'S Z 'S l # Octal Bus Transceivers with inverted 3-state outputs Octal Bus Transceivers (with 3-state outputs) This octal bus transceiver is designed for asynchronous twoway com munication between data buses. The control

Contextual Info: H I T A C H I / LOGI C / A R R A Y S/ M E M =12 » E g 44LlbdÏÏd“ üGl D4QS S | ~ — . 92 D HD74HC160 HD74HC161 HD74HC162 HD74HC163 1040 5 D I ~ ^ S - Z 3 -0 5 # HD74HC160-Synchronous Decade Counter D ire c t Clear

Contextual Info: H I T A C H I / LOGIC/ARRAYS/riEfl TE D Ê | 4 4^^5 03 0 □ 1 □ 4 01 ô |~~ 92D HD74HC155 # 10401 D T 'iû ^ - a i >55" Dual 2-to-4-line Decoders/Dem ultiplexers This circuit features dual 1-line-to-4-line dem ultiplexer with | I PIN ARRANGEMENT individual strobes and common binary-address input. When

Contextual Info: HITACHI/ L O G I C / A R R A Y S / M E M 12 HD74HC157 HD74HC158 B E I 4iHbaG3 0P104CI3 1 | ~ . 92D 1 04 03 D 7 ^ 7 -.2 /-£ / # Quad. 2-to-1-line Data Selectors/Multiplexers with noninverted outputs # Quad. 2-to-l-line Data Selectors/Multiplexers (with inverted outputs)

Contextual Info: HITACHI/ L O G I C / A RR AYS/ ME M ^5 DÊ] DfllGMhB fl 92D HD74HC245 # D T 'S % '3 f 10463 Octal Bu s Transceivers with 3-state outputs Each device has an active low enable input G and a direction control input, D IR . When D IR is high, data flows from the

Contextual Info: HM51W17805B Series 2,097,152-word x 8-bit Dynamic Random Access Memory HITACHI ADE-203-462B Z Rev. 2.0 May. 30,1996 Description The Hitachi HM51W17805B is a CMOS dynamic RAM organized 2,097,152-word X 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM51W17805B offers

Contextual Info: H M 5 1 4 1 O O C /C L S e r i e s Preliminary 4,194,304-word x 1-bit Dynamic Random Access Memory HITACHI T he H ita c h i H M 514100C is a CM OS dynam ic R A M o rg a n iz e d 4 ,1 9 4 ,3 0 4 w o rds x 1 b its . HM 514100C has realized higher density, higher

Contextual Info: HD61202- D ot M atrix Liquid Crystal Graphic D isp lay Colum n Driver Features Description HD61202 is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores the display data transferred from a 8-bit

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

Contextual Info: Section 1 H8S/2245 Series Features 1.1 H8S/2245 Series Functions H8S/2245 Series microcomputers are designed for faster instruction execution, using a realtime control oriented CPU with an internal 32bit architecture, and can run programs based on the C high-level language efficiently. As well as large-capacity ROM and RAM, these microcomputers