432P Search Results

432W6

Abstract: QTP432-T-3232-0 432P
Contextual Info: 432W6 Plastic 432pin 32✕32mm Body QTP EIAJ Package Code QTP432-T-3232-0.25 Weight g JEDEC Code – 4.75±0.05 69.95±0.2 63.95±0.08 B 57.75±0.08 56.2±0.08 0.65±0.05 0.4±0.03 0.8±0.03 1.98±0.03 0.5±0.05 1.98±0.03 Detail A 0.1±0.05 D 56.2±0.08

232P6W

Abstract: EARTHING
Contextual Info: Plugs IP67 32 A Enclosure : Thermoplastic polyester PBT Cable entry : Compression gland Cable area for 32 A : 2.5 - 6.0 mm2 Terminals/ Poles 2P+E 3P+N+E Type Earthing position 232P6W 6h 432P6W 6h Color code Blue Red Voltage Frequency Order Code Pack. Weight Rated

00XXX001

Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic

LTD-482

Abstract: 7 Segment Displays 3 Digit common anode led 7 segment common anode 7 segment common anode connection 7 segment led 1.2 inch LTD-432E LTD-432GC LTD432PC LTD-432 ltd432gc
Contextual Info: 0.4" Dual Digit Numeric LED Displays LTD-432 LTD-482 Features Series Package Dimensions 0.4 inch 10.21mm digit height Continuous uniform segments. Choices of three bright colors-bright red/green/red orange. Low power requirement. Excellent characters appearance.

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Famüies Features Cadence, Escalade, Exemplar, 1ST, M entor Graphics, Synopsys and Viewlogic High C a p a c ity • JTAG1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

Atlas V quantum

Abstract: 132217 RCA-Y PM7324 Atlas IV quantum wsa0
Contextual Info: PM7324 S/UNI-ATLAS S/UNI-ATLAS DATASHEET PMC-1971154 ISSUE 7 S/UNI-ATM LAYER SOLUTION PM7324 S/UNI-ATLAS SATURN USER NETWORK INTERFACE ATM LAYER SOLUTION DATASHEET ISSUE 7: JANUARY, 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

radix-8 FFT

Abstract: yswa BR17 CI23 radix DSP24 24PORTB DR17 64 point radix 4 FFT dsp24s
Contextual Info: DSP Architectures Transform Your World DSP24 TM High Performance Scalable DSP Chip DSP Architectures Data Sheet Real 24 PORT A Imag 24 DSP24 Imag 24 24 24 X I NP U TB US Y INPUT BU S OUTPU TB US 24 48 Imag 24 Scheduler/ Controller X Y Memory A 24 Memory B

DY6009

Abstract: DY6020 DY6035 DY6055 DynaChip IO258 dy6000-family
Contextual Info: DY6000 Family FAST Field Programmable Gate Array™ Features • • • • • • • • • • • • • • • • • • • • • Predictable, Fast, Patented Active Repeater™ Architecture I/O Data-Transfer Rates up to 200MHz 2.7ns I/O Clock-to-Output Time with 10pf Load;

Field-Programmable Gate Arrays

Abstract: MPC8260 MPC860
Contextual Info: Product Brief January 15, 2002 ORCA Series 4 Field-Programmable Gate Arrays Introduction • Traditional I/O selections: — LVTTL and LVCMOS 3.3 V, 2.5 V, and 1.8 V I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability:

OR2C12A

Abstract: ps304 S208 ATT2C
Contextual Info: Product Brief January 2002 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology

TOSHIBA TC160G

Abstract: Toshiba NAND 67 Bga 568ps tc160g TC190G04 tc170g TC190G TC190G02 TC190G10 C2878
Contextual Info: TOSHIBA System ASIC TC190 Series CMOS ASICs 0.6µ 3.0/3.3V ASIC Family The 0.6µm, 5V TC190 ASIC series provides higher system performance and device integration with lower power than previous generation 5V families. Highly accurate delay models, area efficient memory cells and a very fine pitch TAB bonding capability

CT-GWC

Abstract: CT-GWC3336 entropia entropia api Centillium Communications POS-PHY ATM format G.729
Contextual Info: Entropia CT-GWC3336 Voice Processor Features — Comfort noise generation CNG — Per channel A-law and µ-law support and conversion — Automatic detection of fax/data modem calls and revert to 64 kbps PCM — Comprehensive tone detection and processing for

LUCENT 277

Abstract: ci 7495 intel FPGA CI LM 555
Contextual Info: Product Brief November 1999 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Features • Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay.

XC95144

Abstract: XC9500 XC95108 XC95180 XC95216 XC9536 XC9572 2-bit adder layout xapp x5878
Contextual Info:  Designing with XC9500 CPLDs XAPP 073 - January, 1997 Version 1.0 Application Note Summary This application note will help designers understand the XC9500 architecture and how to get the best performance from these devices. Xilinx Family XC9500 Introduction

IC TTL 7495 diagram and truth table

Abstract: BA 5979 S AM 5766 BA 5979 motorola s240 pin diagram of ic 7495 Xilinx counter transistor on 4409 PR25D inverter design using plc
Contextual Info: Data Sheet June 1999 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in

A7721

Abstract: A7817 int1200 h30 tb15 A7801 IXP1200 a7737 a7741 a4772-01 A7747
Contextual Info: IXP1200 Network Processor Datasheet Product Features The IXP1200 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1200 are the performance of ASIC hardware

PT35c transistor

Abstract: pt35c transistor pt36c me 4946 PBGA PR25D transistor on 4409 307-45 4946 ah lm 458 ic
Contextual Info: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction This data addendum refers to the information found in the ORCA® Series 3C and 3T Field-Programmable Gate Arrays Data Sheet. • ■ Features ■ ■ ■ ■ ■ ■

BA 5979 S

Abstract: or3t806ba352-db 2764 EEPROM BA 5979 BL06 transistor OR3T125 OR3T20 OR3T30 OR3T55 PT10
Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 m OR3C and 0.3 μm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in

led 7 segment anode 5101

Abstract: Q002 432PC y413 lto432xc
Contextual Info: ] f ." E C ]3 482SC SE R IE S .] ! T 1 0.4" D U A L D IG IT N U M ER IC D IS P L A Y S |LITE-0N INC 31E D 553b3b? 0002400 3 . -•'t ILTN FEA TU RES • 0.4 INCH 10.21 mm D IGIT HEIGHT. • CONTINUOUS UNIFORM SEGMENTS. • CHOICE OF FOUR BRIGHT C O L O R S -R E D /

PT15D

Abstract: OR2T40A-6PS208I R4C18
Contextual Info: Data Sheet August 2002 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology

vhdl code for pcm bit stream generator

Contextual Info: Preliminary Data Sheet January 2002 ORCA ORT4622 Field-Programmable System Chip FPSC Four-Channel x 622 Mbits/s Backplane Transceiver Introduction Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high-speed serial backplane data transfer. The 622 Mbits/s backplane transceiver offers a clockless, high-speed interface for

LATTICE 3000 family

Contextual Info: Lattice Overview include conventional gate-arrays, standard cells and full custom logic circuits , and PLDs. General Lattice Semiconductor Corporation designs, develops and markets high performance programmable logic devices PLDs) and related development system software.

BA 5979

Abstract: br06 lm 398- SAMPLE AND HOLD OR3T125 OR3T20 OR3T30 OR3T55 PT10 diagram for 3 bits binary multiplier circuit ic 7490 truth table
Contextual Info: Data Sheet March 2002 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm OR3C and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in