405BL Search Results

27CS12

Abstract: 27C256-200V10 27C126 27c256-200 D27c256b intel 27126 intel PLD 27C256
Contextual Info: INTEL CORP flEflORY/PLD/ 44E D 405bl7b GDVIS^ ' T 7% in ta l T • ITL2 ' ß - 2 ci 27C256 256K (32K x 8 CHMOS EPROM High Speed — 120 ns Access Time Low Power Consumption — 100 /xA Standby, 30 mA Active Fast Programming — Quick-Pulse Programming

Contextual Info: in te i ADVANCE INFORMATION 28F016XS 16-MBIT 1 MBIT x 16, 2 MBIT x 8 SYNCHRONOUS FLASH MEMORY • Effective Zero Wait-State Performance up to 33 MHz — Synchronous Pipelined Reads ■ SmartVoltage Technology — User-Selectable 3.3V or 5V V cc — User-Selectable 5V or 12V Vpp

51FFH

Contextual Info: in te i 82092AA PCI TO PCMCIA/ENHANCED-IDE CONTROLLER • Provides the Ultimate Plug and Play Solution fo r High Perform ance PCI Desktop Systems — Supports Combinations of PCMCIA and Enhanced Local Bus IDE Interfaces — Contains a 32-bit PCI Local Bus

Contextual Info: P R is y iif iiO K iÆ in r in ie l VE28F008 8 MBIT (1 MBIT x 8 FLASH MEMORY • High-Density Symmetrically Blocked Architecture — Sixteen 64 Kbyte Blocks Very High-Performance Read — 95 ns Maximum Access Time ■ Avionics Temperature Range 40°C to + 125°C

FDS 4468

Abstract: HBT 01 - 04G INTEL 486 sx sl pinout 240950 JVC 4580 fds 4418 TOT - 4301 INTEL DX4 241199 Intel DX4TM
Contextual Info: intj, INTEL486 PROCESSOR FAMILY • Write-Back Enhanced lntelDX4™ Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

8086 opcode sheet with mnemonics free

Abstract: 1226d 80286 microprocessor pin out diagram 8086 Programmers Reference Manual 8086 opcode sheet free 80287 microprocessor block diagram and pin diagram Opcode list of 8086 microprocessor 80287
Contextual Info: intgl lntel387TM DX MATH COPROCESSOR High Performance 80-Bit Internal Architecture • Upward Object-Code Compatible from 8087 and 80287 Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic l Full-Range Transcendental Operations for SINE, COSINE, TANGENT,

d5017

Abstract: schematic diagram 555 PAM 82820 mch chip 8-pin H049 obd usb api 4st 03 82820 GAR7 H027 MLT 22 542
Contextual Info: intei Intel 820 Chipset: 82820 Memory Controller Hub MCH Datasheet November 1999 Order Number: 290630-001 Mfl2bl75 GEGTTlb Ö5Ö • Intef* 82820 MCH intel. Information in this docum ent is provided In connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

82378IB

Abstract: 82378 apm 8105 ISA/AD 945 SFH 6711 SGDA 290473 BA9S 82C37 82C37A
Contextual Info: O M F Q 3 M rO (M 82378 SYSTEM I/O (SIO • Provides the Bridge Between the PCI Bus and ISA Bus ■ 100% PCI and ISA Compatible — PCI and ISA Master/Slave Interface — Directly Drives 10 PCI Loads and 6 ISA Slots — Supports PCI at 25 MHz and 33 MHz

8251 microprocessor block diagram

Abstract: intel 8251 USART block diagram 8251A intel 8251 INTEL USART 8251 intel 8251 USART control word format 8251 intel features of 8251 microprocessor Intel 8080 instruction set INTEL 8251A USART
Contextual Info: INTEL CORP MEMORY/PL] / 44E D m 4û2bl7b 0073434 T EI ITL B inteJ. 8251A PROGRAMMABLE CO M U M ICA TiO N IN TERFA CE • Synchro no us and A synchronous Operation A syn chron o u s Baud Rate— DC to 19.2K Baud ■ Synchro no us 5 - 8 Bit C haracters; Internal or External Character

Contextual Info: PRODUCT PREVIEW in te l BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT 28F004S3, 28F008S3, 28F016S3 Includes Commercialand Extended Temperature Specifications SmartVoltage Technology — Smart 3 Flash: 2.7V Read-Only or 3.3V Vcc and 3.3V or 12V VPP

I960 mx

Abstract: 271194 marking A17 DIODE marking ED BDATA23 i960mx 27119
Contextual Info: In te l. MILITARY i960 MM/MX SUPERSCALAR MICROPROCESSOR Implements JIAWG 32-bit ISA Standard i960® MX Processor Only High-Performance 32-bit Superscalar Architecture — Up to Three Instructions per Clock Execution — Five Parallel Execution Units — Load/Store Architecture

ma6351

Abstract: LE-24T ZO 607MA A82496 290446 EM 5135 diode 522110 jp 486TM 241429 dm4021
Contextual Info: INTEL CORP -CUP/PRPHLSJ S7E D • 4 fl2 bl 7 5 01522147 t»23 ■ in te l Pentium Processor User's Manual Volume 2: 82496 Cache Controller and 82491 Cache SRAM Data Book NOTE: The Pentium™ Processor User's Manual consists of three books: Pentium™ Processor Data Book, Order Number 241428; the

80C452-1

Abstract: DIA DB3
Contextual Info: ’r INTEL CORP UP/PRPHLS intgl 31E D ~ ' - -r.-' • 402bli7S OQfl'ifim 5 ■ 9 r - ? 2 - 3 Z - ir UPI-452 CHMOS PROGRAMMABLE I/O PROCESSOR 83C452 - 8K x 8 Mask Programmable Internal ROM 80C452-External ROM/EPROM 83C452/80C452:3.5 to 14 MHz Clock Rate Software Compatible with the MCS-51

TCS 4199

Abstract: M80C186
Contextual Info: tF ^ m L O G M M V in te i M28F010 1024K 128K x 8 CMOS FLASH MEMORY ETOX-III Flash-Memory Technology — EPROM-Compatible Process Base — High-Volume Manufacturing Experience Compatible with JEDEC-Standard Byte-Wide EPROM Pinouts 10,000 Program/Erase Cycles Minimum

PLD intel

Abstract: intel 28F010 07B27 interfacing eprom and eeprom 28f010-150 intel PLD
Contextual Info: INTEL CORP MEMORY/PL] / SbE I 4fl2bl7b Q07bBbl T i l « I T L P in te l 28F010 1024K (128K x 8) CMOS FLASH MEMORY Flash Electrical Chip-Erase — 1 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jas Typical Byte-Program — 2 Second Chip-Program

SmartDie

Abstract: 271296 ALi Corporation M1431
Contextual Info: in te i 28F008SA-L 8-MBIT 1 MBIT x 8 F L A S H F IL E T M High-Density Symmetrically-Blocked Architecture — Sixteen 64-Kbyte Blocks Low-Voltage Operation 3.3V + 0.3V or 5.0V ±10% Vcc Extended Cycling Capability — 10,000 Block Erase Cycles — 160,000 Block Erase

Contextual Info: A E M f t N I ! ! O M IF © fô [M A ? fl@ M 8XL51FA/FB/FC LOW VOLTAGE CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS Commercial/Express • m ■ ■ ■ m High Performance CHMOS OTP ROM/ ■ Boolean Processor

Contextual Info: in y CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server PTS interrupts. It discusses the three special interrupts and the sev­ en PTS modes, four of which are used with the EPA to provide a software serial I/O channel for

Contextual Info: irrigl PRELIMINARY 4-MBIT 256K X 16, 512K X 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B 28F400CE-T/B, 28F004BE-T/B Intel SmartVoltage Technology — 5V or 12V Program/Erase — 2.7V, 3.3V or 5V Read Operation — Increased Programming Throughput

PCCB

Contextual Info: INTEL CORP UP/PRPHLS 5DE Q M 1« 432^175 M M OOfilTOS S • ! O ^ H F iO ^ M O ® liO In te l M8097BH, M8397BH, M8797BH ADVANCED 16-BIT MICROCONTROLLER WITH 8- OR 16-BIT EXTERNAL BUS ' Military <-* ‘ 1 ^>I ■ M8797BH: an M8097BH with 8K Bytes of On-Chip EPROM

01ag

Abstract: ML616
Contextual Info: in te l CHAPTER 3 INSTRUCTION SET REFERENCE This chapter describes the complete Intel Architecture instruction set, including the integer, floating-point, MMX technology, and system instructions. The instruction descriptions are arranged in alphabetical order. For each instruction, the forms are given for each operand combi­

GIGABYTE G41

Abstract: 82360SL intel 82360SL
Contextual Info: INTEL CORP UP/PRPHLS 3IE D 402tl7S 00aSbb7 2 int@l 7 = V f-/7 -^ 2 386TM SL MICROPROCESSOR SuperSet Highly-Integrated Static 386 Microprocessor Complete ISA Peripheral Subsystem System-Wide Power Management Static 386™ CPU Core — Runs MS-DOS*, WINDOWS*, O S/2*

80c186ec

Abstract: DDA10
Contextual Info: INTEL CORP UP/PRPHLS MME D m Mfl5bl7S Q 1 0 S 1 3 b 7 • I T U ra @ (U ) T [ p [^ i¥ 0 llW in te l - T ^ q - n - i ô 80C186EC-16, -13 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR . ■ Full Static Operation ■ True CMOS Inputs and Outputs ■ : —40°C to +85°C Operating Temperature Range

HBT 01 - 04G

Abstract: HBT 00 - 04G INTEL DX4 86-1-S smi LT 9636 INTEL DX2 1184N gi 9214 80286 instruction set 22-31N
Contextual Info: in te i MILITARY Intel486 PROCESSOR FAMILY • lntelDX4™ Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant