4 BIT BISTABLE LATCH DEVICE Search Results

PIN CONFIGURATION 7475

Abstract: Equivalent 74LS75 TTL 7475 7475 D latch 74LS75 7475 Quad bistable latches pin configuration
Contextual Info: 7475, LS75 Signelics Latches Quad Bistable Latch Product Specification Logic Products FEATURES • 4-bit bistable latch • Refer to 74LS375 for Vcc and GND on corner pins DESCRIPTION The '75 has four bistable latches. Each 2-bit latch is controlled by an active

PIN CONFIGURATION 7475

Abstract: 7475 D latch LS 7475 7475 Quad bistable latches pin configuration pin configuration of 7475 TTL 7475 7475 7475 data latch pin diagram 7475 pin diagram of 7475
Contextual Info: 7475, LS75 Signetics Latches Quad Bistable Latch Product Specification Logic Products FEATURES TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 7475 18ns (tpi_n) 9ns ( t PHL) 32mA 74LS75 15ns (tpLH) 9ns (t p h l ) 6.3mA TYPE • 4-bit bistable latch

54HC

Abstract: 54LS 74HC 74LS C1995 MM54HC75 MM54HC75J MM74HC75 MM74HC75J
Contextual Info: MM54HC75 MM74HC75 4-Bit Bistable Latch with Q and Q Output General Description This 4-bit latch utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption normally associated with standard CMOS integrated circuits These devices can drive 10 LS-TTL loads

Contextual Info: January 1988 Semiconductor MM54HC75/MM74HC75 _ 4-Bit Bistable Latch with Q and Q Output General Description This 4-bit latch utilizes advanced silicon-gate CMOS tech­ nology to achieve the high noise immunity and low power consumption normally associated with standard CMOS inte­

Contextual Info: January 1988 S em ic o nd u cto r MM54HC75/MM74HC75 _ 4-Bit Bistable Latch with Q and Q Output General Description This 4-bit latch utilizes advanced silicon-gate CMOS tech­ nology to achieve the high noise immunity and low power consumption normally associated with standard CMOS inte­

Contextual Info: M M OTOROLA Military 54LS375 4-Bit Bistable Latch ELECTRICALLY TESTED PER: MIL-M-38510/31604 The 54LS375 is a 4-bit D-Type Latch for use as tem porary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the

5303-1

Abstract: 74HC MM54HC MM54HC75 MM74HC MM74HC75
Contextual Info: January 1988 Semiconductor MM54HC75/MM74HC75 _ 4-Bit Bistable Latch with Q and Q Output General Description This 4-bit latch utilizes advanced silicon-gate CMOS te c h ­ nology to achieve th e high noise im m unity and low pow er consum ption norm ally associated w ith standard CM OS inte ­

GD74HCT75

Contextual Info: GD54/74HC75, GD54/74HCT75 DUAL 2-BIT 4-BIT BISTABLE LATCHES General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 5 . They consist of two independent 2-bit transparent latches. This latch is suited for use as a temporary storage of binary information. Informa­

54LS75

Abstract: 1N3064 54LS375 DRD4
Contextual Info: g Military 54LS75 MOTOROLA 4-Bit Bistable Latch With Q and Q MPO unni ELECTRICALLY TESTED PER: MIL-M-38510/31601 The 54LS75 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. Information present at the data (D) input is transferred to

Contextual Info: g Military 54LS75 MOTOROLA 4-Bit Bistable Latch With Q and Q ELECTRICALLY TESTED PER: MIL-M-38510/31601 M The 54LS75 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. Information present at the data (D) input is transferred to

1N3064

Abstract: 54LS375 2E124
Contextual Info: M M O T O R O L A Military 54LS375 4-Bit Bistable Latch ELECTRICALLY TESTED PER: Ml L-M-38510/31604 The 54LS375 is a 4-bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the

74ls75

Abstract: 74ls75 pin configuration
Contextual Info: GD54/74LS75 4-BIT BISTABLE LATCH Features • Enable inputs common to two circuits each • Q ad Q outputs Pin Configuration ENABLE INPUT OUTPUTS 1Q 2Q 2C 1-2E GND 3 d f t t 4 — Description Function Table 4Q r~fH=L— YT i. T This device contains 4 D-type latch circuits and is

74LS75

Contextual Info: GD54/74LS75 4-BIT BISTABLE LATCH Features • • Enable inputs common to two circuits each Q a d Q outputs Pin Configuration ENABLE INPUT OUTPUTS 1Q 2Q 20 t t 1 1-2E GND 3 0 4 3Q 1 t 4Q t trV n Description This device contains 4 D-type latch circuits and is

Contextual Info: M M O T O R O L A M ilitary 54LS375 4-Bit Bistable Latch ELECTRICALLY TESTED PER: Ml L-M-38510/31604 HPO mm The 54LS375 is a 4-bit D-Type Latch for use as temporary storage for binary information between processing limits and input/output or indicator units. When the Enable (E) is HIGH, information present at the

DP-14

Abstract: FP-14DA FP-14DN HD74HC77 TTP-14D Hitachi DSA00220
Contextual Info: HD74HC77 4-bit Bistable Latch ADE-205-424 Z 1st. Edition Sep. 2000 Description The HD74HC77 is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q

LS 7475

Abstract: C4408
Contextual Info: SN5475, SN5477, SN54LS75, SN54LS77. SN7475, SN74LS75 4 BIT BISTABLE LATCHES MAR CH 1 9 7 4 - each latch (TOP VIEW) OUTPUTS INPUTS REVISED M A R C H 1 9 8 8 SN 5475 , SN 54LS75 . . . J OR W PACKAGE S N 7475 . . . N PACKAGE SN 74LS 75 . . . D O R N PACKAGE

Contextual Info: TYPES SN5475, SN5477, SN54L75, SN54L77, SN54LS75, SN54LS77, SN7475, SN74LS75 4-BIT BISTABLE LATCHES M ARCH logic each latch INPUTS C (TOP VIEW) OUTPUTS a L H L H H H X L Qo 1983 SN547&, SN54LS75 . . . J OR W PACKAGE SN 54L75 . . . J PACKAGE SN 7475 . . . J OR N PACKAGE

SN74LS75 pin diagram

Abstract: 54LS 74LS LS75 SN5475 SN5477 SN54LS75 SN54LS77 SN7475 SN74LS75
Contextual Info: SN5475, SN5477, SN54LS75. SN54LS77, S N7475, SN74LS75 4-BIT BISTABLE LATCHES SDLS120 MARCH 1974 - REVISED MARCH 1988 F U N C TIO N TABLE S N 5 4 7 5 , S N 54LS 75 . . . J OR W PACKAGE S N 7 4 7 5 . . . N PACKAGE S N 74LS 75 . . . D OR N PACKAGE each latch

Contextual Info: HITACHI/ L O G I C / A RRAYS/ NEN ^2 HD74HC77 D E | 44TL,203 0010340 Ö 92D 10348 D T-46-07-Ö 9 • 4-bit Bistable Latch The H D 74H C77 is ideally suited fo r use as temporary storage | PIN ARRANGEMENT fo r binary inform ation between processing units and input/

HD74HC77

Abstract: HD74HC77FPEL HD74HC77P HD74HC77RPEL PRDP0014AB-B PRSP0014DF-B
Contextual Info: HD74HC77 4-bit Bistable Latch REJ03D0552-0200 Previous ADE-205-424 Rev.2.00 Oct 06, 2005 Description The HD74HC77 is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable

54LS

Abstract: 74LS LS75 SN5475 SN5477 SN54LS75 SN54LS77 SN7475 SN74LS75 ls-77
Contextual Info: SN5475, SN5477, SN54LS75, SN54LS77, SN7475, SN74LS75 4-BIT BISTABLE LATCHES MARCH 1974 - REVISED MARCH 1988 S N 5 4 7 5 . S N 5 4 L S 7 5 . . . J OR W P A C K A G E SN 7475 . NPACKAGE SN 74LS75 . . . D OR N PACKAGE F U N C TIO N T A B L E e a ch latch IN P U T S

DP-14

Abstract: FP-14DA FP-14DN HD74HC77 TTP-14D Hitachi DSA00396
Contextual Info: HD74HC77 4-bit Bistable Latch Description The HD74HC77 is ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains

Contextual Info: SN54HC75, SN74HC75 4 BIT BISTABLE LATCHES D2684. D EC EM B ER 1982 • Complimentary Q and Q Outputs • Package Options Include Plastic "Sm all Outline" Packages, Standard Plastic and Ceramic 300-mii DIPs • Dependable Texas Instruments Quality and Reliability

SN54HC

Abstract: 74HC77
Contextual Info: SN54HC77, SN74HC77 4 BIT BISTABLE LATCHES D2684 DECEMBER 1952 - REV'SED SEPTEJVSER 1.9S7 • • I I O u tlin e " P a c k a g e s , Sta n d a rd P la stic C e ra m ic 3 0 0 -m il D IPs • I P a c k a g e O p tio n s In clu de P la stic " S m a ll SN 54H C 77 . . . J P A C KA G E