4 BIT Search Results

74LS340

Abstract: 74ls310 74ls344 74LS210 74LS341 74S210 74L310 ls344 74LS31 74s310
Contextual Info: 8-Bit Buffers with Schmitt Trigger Inputs Features S N 5 4 /7 4 L S 3 1 0 S N 5 4 /7 4 S 3 1 0 S N 5 4 /7 4 L S 3 4 0 S N 5 4 /7 4 S 3 4 0 S N 5 4 /7 4 L S 3 4 1 S N 5 4 /7 4 S 3 4 1 S N 5 4 /7 4 L S 3 4 4 S N 5 4 /7 4 S 3 4 4 Ordering Information • Schmitt-trigger Inputs guarantee high noise margin

FP-80B

Contextual Info: H D 4 0 4 8 1 8 /H D 4 0 4 8 1 4 /H D 4 0 7 4 8 1 8 — H D 4 0 L 4 8 1 8 /H D 4 0 L 4 8 1 4 /H D 4 0 7 L 4 8 1 8 Description T he H D 4 04 8 1 8 /H D 4 0 4 81 4 /H D 40 7 4 8 18/ HD40L4818/HD40L4814/HD407L4818 is a 4-bit single-chip HMCS400 series microcomputer

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ;iP D 4 5 6 4 4 4 1 , 4 5 6 4 8 4 1 , 4 5 6 4 1 6 3 64M-bit Synchronous DRAM 4-bank, LVTTL Description The ,uPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4, 1,048,576 x16 x 4 word x bit x bank , respectively.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ju P D 4 5 6 4 4 4 1 ,4 5 6 4 8 4 1 , 4 5 6 4 1 6 3 64 M-bit Synchronous DRAM 4-bank, LVTTL Description The ,uPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynam ic random-access memories, organized as 4,194,304x4x4, 2,097,152x8x4, 1,048,576x16x4 word x bit x bank , respectively.

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT /¿ P D 4 5 6 4 4 4 1 -A 7 5 , 4 5 6 4 8 4 1 -A 7 5 64M-bit Synchronous DRAM, 133MHz 4-bank, LVTTL Description The ^¡PD4564441-A75, 4564841-A75 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4 and 2,097,152 x 8 x 4 word x bit x bank , respectively.

HM472114P-3

Abstract: 2114L HM472114-3 HM472114-4 HM472114P-4
Contextual Info: H M 4 7 2 1 14 -3 ,H M 4 7 2 1 14-4, H M 4 7 2 1 1 4 P -3 ,H M 4 7 2 1 1 4 P -4 1024-word X 4-bit Static Random Access Memory • Fast Access T im e .* . • L o w O pe ratin g Pow er .

Contextual Info: HB56UW472EJN Series, HB56UW464EJN Series HB56UW472EJN 32 MB Unbuffered EDO DRAM DIMM 4-Mword X 72-bit, 4 k Refresh, 1-Bank Module 18 pcs of 4 M X 4 Components HB56UW464EJN 32 MB Unbuffered EDO DRAM DIMM 4-Mword X 64-bit, 4 k Refresh, 1-Bank Module (16 pcs of 4 M X 4 Components)

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 4 5 1 4 B P , T C 4 5 1 5 B TC4514BP 4-BIT LATCH/4-T0-16 LINE DECODER Output Active High Option TC4515BP 4-BIT LATCH/4-T0-16 LINE DECODER (Output Active Low Option) TC4514BP and TC4515BP are decoders which convert 4

CB-68LP

Abstract: MIO-16E-4 SH6868 PCI-MIO-16E-4 PXI-6040E 77723
Contextual Info: PCI-MIO-16E-4, PXI-6040E, DAQCard-AI-16E-4, NEC-MIO-16E-4, NEC-AI-16E-4 E Series Multifunction I/O – 250 kS/s, 12-Bit, 16 Analog Inputs PCI-MIO-16E-4, PXI-6040E, DAQCard-AI-16E-4, NEC-MIO-16E-4, NEC-AI-16E-4 Analog Input 16 single-ended, 8 differential channels

1170 T

Abstract: 24C02 HB56UW464EJN HB56UW472EJN HB56UW472EJN-5 HB56UW472EJN-5L HB56UW472EJN-6 HB56UW472EJN-6L HB56UW472EJN-7 HM51W16405
Contextual Info: HB56UW472EJN Series, HB56UW464EJN Series HB56UW472EJN 32 MB Unbuffered EDO DRAM DIMM 4-Mword x 72-bit, 4 k Refresh, 1-Bank Module 18 pcs of 4 M × 4 Components HB56UW464EJN 32 MB Unbuffered EDO DRAM DIMM 4-Mword × 64-bit, 4 k Refresh, 1-Bank Module (16 pcs of 4 M × 4 Components)

Contextual Info: KM44C4100 CMOS DRAM 4M X 4 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Perform ance range: The Samsung K M 4 4 C 4 1 00 is a high speed CMOS 4 ,1 9 4 ,3 0 4 X 4 Dynamic Random Access Memory. Its design is optimized for high performance applications

W9425G6JH

Contextual Info: W9425G6JH 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

PCI-MIO-16E-4

Abstract: CB-68LP
Contextual Info: PCI-MIO-16E-4, PXI-6040E, DAQCard-AI-16E-4, NEC-MIO-16E-4, NEC-AI-16E-4 E Series Multifunction I/O – 250 kS/s, 12-Bit, 16 Analog Inputs PCI-MIO-16E-4, PXI-6040E, DAQCard-AI-16E-4, NEC-MIO-16E-4, NEC-AI-16E-4 Analog Input 16 single-ended, 8 differential channels

ci 4410

Abstract: 4410
Contextual Info: MITSUBISHI LSIs M 5 M 4 4 4 1 O A W J, J , L , T P , R T - 6 , -7 , - 8 , - I O FAST PAGE MODE 4 1 9 4 3 0 4 -B IT 1 0 4 8 5 7 6 -W 0 R D B Y 4-BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a family of 1048576-word by 4-bit dynamic RAM S,

D45128841G5-A80

Contextual Info: PRELIMINARY DATA SHEET / - N E C ^ MOS INTEGRATED CIRCUIT _ / /¿ P D 4 5 1 2 8 4 4 1 ,4 5 1 2 8 8 4 1 , 4 5 1 2 8 1 6 3 128 M-bit Synchronous DRAM

Contextual Info: Multiformat 11-Bit HDTV Video Encoder ADV7322 High definition HD input formats 16-bit, 24-bit (4:2:2, 4:4:4) parallel YCrCb Fully compliant with SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i) RGB in 3-bit x 8-bit 4:4:4 input format

Contextual Info: DATA SHEET NEC / _ / MOS INTEGRATED CIRCUIT /iPD42S16400L, 4216400L, 42S17400L, 4217400L 3.3 V OPERATION 16 M BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, FAST PAGE MODE Description T h e ¿ P D 42S16400L, 4 21 6 4 0 0 L , 4 2 S 1 7 4 0 0 L , 4 2 1 7 4 0 0 L a re 4 194 3 0 4 w o r d s b y 4 b its d y n a m ic C M O S R A M s .

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ju P D 4 2 S 1 6 4 0 5 L , 4 2 1 6 4 0 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The //PD42S16405L, 4216405L are 4 194 304 words by 4 bits dynamic CMOS RAMs with optional hyper page

HM472114AP-2

Abstract: HM472114A HM472114A-2 2114L HM472114A-1 HM472114AP-1 HM472114AP2
Contextual Info: H M 472114A -1 ,H M 4 7 2 1 1 4 A -2 , H M 472114A P-1 ,H M 4 7 2 1 1 4 A P -2 1 0 2 4 -word X 4 - bit Static Random Access M em ory Fast Access T i m e . H M 4 72 114 A -1 150ns max. H M 4 7 2 1 1 4 A -2 200ns (m ax.)

54194

Abstract: SN74194 S194 SN54194 SN54LS194A SN54S194 SN74LS194A SN74S194
Contextual Info: TYPES SN54194, SN54LS194A, SN54S194, SN74194, SN74LS194A, SN74S194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS M AR CH 1 9 7 4 -R E V IS E D APRIL 1 9 8 5 S N 5 4 1 9 4 , S N 5 4 L S 1 9 4 A , S N 5 4 S 1 9 4 . . . J OR W PAC KAG E Parallel Inputs and O utputs

ADV7197EB

Abstract: ADV7197EB Rev. B 720P ADV7197 ADV7197KST RS-170 RS-343A tri-level sync generator OP AMP 748 MR520
Contextual Info: a FEATURES INPUT FORMATS YCrCb in 2 ؋ 10-Bit 4:2:2 or 3 ؋ 10-Bit (4:4:4) Format Compliant to SMPTE274M (1080i), SMPTE296M (720p) and Any Other High-Definition Standard Using Async Timing Mode RGB in 3 ؋ 10-Bit 4:4:4 Format OUTPUT FORMATS YPrPb HDTV (EIA-770.3)

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT jU P D 4 5 2 5 6 4 4 1 , 4 5 2 5 6 8 4 1 , 4 5 2 5 6 1 6 3 256M-bit Synchronous DRAM 4-bank, LVTTL Description The ,uPD45256441, 45256841, 45256163 are high-speed 268,435,456 bit synchronous dynamic random-access

Contextual Info: MOS INTEGRATED CIRCUIT ju P D 4 2 S 1 6 4 0 5 L , 4 2 1 6 4 0 5 L 3.3 V OPERATION 16M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The /¿PD42S16405L, 4216405L are 4 194 304 w ords by 4 bits dynam ic C M O S R A M s with optional hyper page

SCR bt 107

Abstract: ADV7321 rgb-rgbhv PAL to ITU-R BT.601/656 Decoder 1080p video DAC equivalent sd 48 41 ITU-R BT.601 720 x 480 hd 22 1080p black test pattern BTA 139
Contextual Info: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs ADV7320/ADV7321 High definition input formats 16-/20-, 24-/30-bit 4:2:2, 4:4:4 parallel YCrCb Fully compliant with: SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i) RGB in 3- x 10-bit 4:4:4 input format