3S33TL Search Results

7202A

Contextual Info: M OSEL V ITEU C MS7200U7201AL/7202AL 256x9,512x9, 1Kx9 CMOS FIFO Features Descriptions • First-In/First-Out static RAM based dual port memory ■ Three densities in a x9 configuration ■ Low power versions ■ Includes empty, full, and half full status flags

Contextual Info: MOSEL VITELIC V53C16258H 256KX 16 PAGE MODE CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT HIGH PERFORMANCE PRELIMINARY 40 45 50 60 Max. R A S Access Time, tf^c 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Time, (tCAA) 20 ns 22 ns 24 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC)

Contextual Info: M O S E L V IT E L IC V53C8257H U LTR A -HIG H SPEED, 256KX 8B IT P A G E M O D E WITH E X TE N D E D DATA O U T P U T ED O A N D C A S B U R S T M O D E CM O S D YN A M IC R A M PR E LIM IN A R Y 45/45L 50/50L 55/55L 60/60L Max. RAS Access Time, Orac)

Contextual Info: M O SE L VITELIC PRELIMINARY V62C518256 32Kx8 BIT STATIC RAM Features Description • High-speed: 35,45, 55, 70 ns ■ Ultra low DC operating current of 5mA Max. ■ Low Power dissipation: TTL Standby: 3mA (Max.) CMOS Standby: 20n.A (Max.) ■ Fully static operation

Contextual Info: M O SEL V tTE LiC V53C8512N 3.3 VOLT, LO W POWER 512K x 8 AN D 5 1 2 K x 9 B IT FA S T PAGE MODE CMOS DYNAMIC RAM PRELIM INARY HIGH PERFORMANCE V53C8512N 60/60L 70/70L M ax. R A S A cce ss T im e, Orac 6 0 ns 70 ns M ax. C o lum n A d dre ss A cce ss T im e , tCAA)

kexz

Contextual Info: MOSEL-VITELIC b2E » MOSEL-VITELIC • b3533Tl GGGS33L. GES ■ M O V I V104J232, V104J236 512K X 32, 512K x 36 SIMM PRELIMINARY Features Description a 524,288 x 32 bit or 524,288 x 36 bit The V104J232 Memory Module is organized as 524,288 x 32 bits in a 72-lead single-in-line module.

mrah

Contextual Info: M O SE L VÊTEUC V53C104N H IG H PERFO RM ANCE, 3.3 VO LT 2 5 6 K X 4 B IT F A S T P A G E M O D E C MOS D YN A M IC R A M HIGH PERFORMANCE V53C104N 60/60L 70/70L 80/80L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, (tCAA)

V53C104D

Contextual Info: M O S E L V IT E U C V53C104D HIGH PERFORMANCE, LO W POWER 256K X 4 B IT FAS T PAG E MODE CMOS DYNAMIC RAM PRELIMINARY 60 HIGH PERFORMANCE V53C104D 70 80 Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns Max. Column Address Access Time, 0CAA) 30 ns 35 ns 40 ns

6264l

Contextual Info: M O SE L VTTEUC M S6264L 8 K x 8 CMOS STATIC RAM Features Description • Available in 70/100 ns Max. ■ Automatic power-down when chip disabled ■ Lower power consumption: MS6264L — 467.5mW (Max.) Operating — 16.5mW (Max.) Standby — 500|iW (Max.) Standby

Contextual Info: M O S E L VITELÊC MS7203U7204L 2K X 9, 4K X 9 CMOS FIFO Features Description • First-In/First-Out static RAM based dual port memory ■ Two densities 2K and 4K in a x9 configuration ■ Low power versions ■ Includes empty, full, and half full status flags

V53C16258H

Abstract: 3bld
Contextual Info: MOSEL VITELIC V53C16258H 256KX 16 PAGE MODE CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT HIGH PERFORMANCE PRELIMINARY 40 45 50 60 Max. R A S Access Time, tf^c 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Time, (tCAA) 20 ns 22 ns 24 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC)

Contextual Info: MOSEL VITELIC V53C511740500 4M X 4 EDO PA GE MODE CMOS DYNAMIC RAM V53C511740500 50 60 70 Max. RAS Access Time, Irac 50 ns 60 ns 70 ns Max. Column Address Access Time, ( ^ aa ) 25 ns 30 ns 35 ns Min. Extended Data Out Page Mode Cycle Time, (fo ) 20 ns 25 ns

Contextual Info: 4öE nOSEL-VITELIC D ^3533^1 MOSEL OOOOfil? novi 4 MS62256B ADVANCE INFORMATION 32K x 8 CMOS Static RAM T -4 6 -2 3 -1 4 FEATURES DESCRIPTION • High-speed - 70/100/120/150 ns The MOSEL MS62256B is a 262,144-bit static random access memory organized as 32,768 words by 8 bits and

Contextual Info: M OSEL VITELIC V53C1 OOF FAMILY HIGH PERFORMANCE, LOW POWER 1M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM 60/60L 70/70L 80/80L Max. RAS Access Time, 0RAC 60 ns 70 ns 80 ns Max. Column Address Access Time, tCAA) 30 ns 35 ns 40 ns Max. CAS Access Time, (tCAC)

v52c4258

Contextual Info: M O S E L V IT E U C V52C4258 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 512X 4 SAM HIGH PERFORMANCE V52C4258 60 70 80 10 60 ns 70 ns 80 ns 100 ns Max. CAS Access Time, tcAc 15 ns 20 ns 25 ns 25 ns Max. Column Address Access Time, ( t^ ) 30 ns 35 ns 40 ns

Contextual Info: M O S E L V IT E L IC V53C16258H HIGH PERFORMANCE 2 5 6 K X 16 EDO PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 30 35 40 45 50 Max. RÂ3 Access Time, Irac 30 ns 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (^ aa) 16 ns 18 ns 20 ns 22 ns 24 ns Min. Extended Data Out Mode Cycle Time, (1pC)

Contextual Info: M O S E L V tT E L iC MS621002A 256K x 4 CMOS STATIC RAM Features Description • ■ ■ ■ ■ ■ ■ ■ The MS621002A is a high speed 1M-bit static RAM organized as 256K x_4. Fully static in operation, the Chip Enable E reduces power to the chip when HIGH. Standby power drops to its

Contextual Info: M O SEL VITELIC V53C808H HIGH PERFORMANCE 1Mx 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM HIGH PERFORM ANCE PRELIMINARY 35 40 45 50 Max. RAS Access Time, tRAc 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (^ aa) 18 ns 20 ns 22 ns 24 ns Min. Extended Data Out Mode Cycle Time, (tpC)