37TA Search Results

Contextual Info: w GEC PLESSEY S I M 1t PRELIMINARY INFORMATION O IN I U C 1 O K S SP5611 1.3GHz BI-DIRECTIONAL l2C BUS CONTROLLED SYNTHESISER Supersedes July 1993 Edition) The SP5611 is a single chip frequency synthesiser designed for TV tuning systems. Control data is entered in the

Contextual Info: P g p GEC PLESSEY S E M I C O N D U C T O R S DS3572-2.3 MA31755 16-BIT FEEDTHROUGH ERROR DETECTION & CORRECTION UNIT EDAC The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory. The EDAC

a13b5

Abstract: A10B11 A15B0 A7B0 A13B4 a5b2
Contextual Info: Mercury Programmable Logic Device Family December 2002, ver. 2.1 Features… Data Sheet • ■ Table 1. Mercury Device Features Feature Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 EP1M350 120,000 350,000 8 18

Contextual Info: P ^ p i G E C P L E S S E Y S E M I C O N D U C T O R S DS3592-4.6 MA28139 OBDH BUS TERMINAL The OBT ASIC will interface any user to the ESA On Board Data Handling bus. Developed under ESA Contract, it conforms to ESA OBDH, Digital Bus Interface and Internal

t2g memory

Abstract: 140U -i6
Contextual Info: AMDÌ1 PRELIMINARY Élan SC300 Highly Integrateci, Low -Power, 32-B it M icrocontroller DISTINCTIVE CHARACTERISTICS • Highly integrated, single-chip CPU and system logic - Optimized for embedded PC applications - Combines 32 bit, x86 compatible, low-voltage

Contextual Info: AMDÌ1 PRELIMINARY Élan SC300 Highly Integrated, Low-Power, 32-Bit Microcontroller DISTINCTIVE CHARACTERISTICS - Zero wait-state access with 70 ns, Page mode DRAMs • Highly integrated, single-chip CPU and system logic - Supports up to 16 Mbyte system memory

Contextual Info: GEC PLESSEY S [ M I O M U C I O K S ADVANCE INFORMATION SL3227 3GHz NPN TRANSISTOR ARRAYS The SL3227 is a monolithic array of the five high frequency low current NPN transistors in a 16 lead DIL package. The transistors exhibit typical ( t of 3GHz and wideband noise

814400

Contextual Info: S i GEC P L E S S E Y PRELIMINARY INFORMATION S E M I C O N D U C T O R S SP8715 1100MHz VERY LOW CURRENT MULTI-MODULUS DIVIDER The SP8715 is a switchable divide by 64/65, 128/129 programmable divider which is guaranteed to operate up to 1100MHz. It will operate from a supply of 2.7V to 5.5V and

LT1007CH

Abstract: LT1037 equivalent C 5588
Contextual Info: L l l I U \ k _ LT1007/LT1037 TECHNOLOGY Low Noise, High Speed Precision O perational Amplifiers F6OTURCS DCSCRIPTIOH • Guaranteed 4.5nV/VHz 10Hz Noise ■ Guaranteed 3.8nV/VHz 1kHz Noise ■ 0.1 Hz to 10Hz Noise, 60nVp.p Typical ■ Guaranteed7 Million Min Voltage Gain, R|_ = 2k

Contextual Info: GEC PLESSEY SEÎ1IC0NDS 31E D 3 7 b0 522 Q D i n t a 1 • 'T 'S O - O 0 ! NJ8821, NJ8821B FREQUENCY SYNTHESISER MICROPROCESSOR INTERFACE WITH RESETTABLE COUNTERS T h e NJ8821 /N J8821B is a synthesiser circuit fabricated on the Plessey 5-m icron C M O S process and is capable of

Contextual Info: GEC PLESSEY S i ADVANCE INFORMATION S L M I L O I N D U C T O R S D.S. 2066 2.1 M V 1815 SINGLE CHIP TELETEXT DECODER FOR 625 LINE OPERATION Superseds June 1990 Edition and Version in Satellite, Cable and T. V. Handbook October 1988 The MV1815 is an advanced CMOS single chip Teletext

thermodisc 37t series

Abstract: bimetal disc 37T bimetal temperature control REFRIGERATION CONTROLS 37ta E29653 37TVG therm-o-disc
Contextual Info: 37T Series Temperature Controls Moisture Resistant Temperature Control The 37T series of 3/4” 19mm bimetal disc temperature controls from Therm-O-Disc offers proven reliability in a moisture resistant sealed design. The snap action of the bimetal disc provides

digital FIR Filter VHDL code

Abstract: verilog code for interpolation filter code iir filter in vhdl verilog code for decimation filter digital FIR Filter verilog code application circuit for FIR filter matlaB design FIR filter matlaB design FIR Filter verilog code 00D8 EP3C16F484C6
Contextual Info: FIR Compiler II MegaCore Function User Guide FIR Compiler II MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01072-2.0 Document last updated for Altera Complete Design Suite version: Document publication date: 10.0 July 2010

atmega128 adc

Abstract: usart in atmega128 2467L PCB ATMEGA128 M103C SP10 SP11 SP12 SP13 SP14
Contextual Info: 产品特点 • 高性能低功耗的 AVR 8 位微处理器 • 先进的 RISC 结构 • • • • • • • – 133 条指令 – 大多数可以在一个时钟周期内完成 – 32 x 8 通用工作寄存器 + 外设控制寄存器 – 全静态工作

A7B0

Abstract: a13b14 A10B A13B4
Contextual Info: Mercury Programmable Logic Device Family March 2002, ver. 2.0 Features… Data Sheet • ■ Table 1. Mercury Device Features Feature Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 EP1M350 120,000 350,000 8 18 4,800

LT1007

Abstract: LT 741 S strain gauge OP07 amplifier
Contextual Info: iT u n m _ LT1Q07/LT1037 TECHNOLOGY Low Noise, High Speed Precision O perational Am plifiers FCRTURCS D C S C R IP TIO n • ■ ■ ■ ■ ■ ■ ■ ■ The LT 1007/LT1037 series features the lowest noise performance available to date for monolithic operational

Contextual Info: G EC PLESSEY SEMICONDS GEC PLESSEY l43E D 37bas22 o a m o s a o b p ls b PRELIM IN ARY IN F O R M A T IO N S E M I C O N D U C T O R S 3048-1.3 ^ T '7 7 - 0 7 - O S SP5054 2.5 GHz 3-WIRE BUS CONTROLLED SYNTHESIZER The SP5054 is a single chip frequency synthesizer

A6B12

Contextual Info: Mercury Programmable Logic Device Family January 2003, ver. 2.2 Features… Data Sheet • ■ Table 1. Mercury Device Features Feature Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 EP1M350 120,000 350,000 8 18

uP 6308 AP

Contextual Info: Si GEC PLESSEY S E M I C O N D U C T O R S SL6609A DIRECT CONVERSION FSK DATA RECEIVER This device is an advanced direct conversion receiver for operation up to 470MHz. The design is based on the SL6609 receiver and is a pin for pin product upgrade. The device

a2b5

Abstract: A12B15 EP1M120 A7B9 A10B8 A15B6 56-LVTTL
Contextual Info: Mercury Programmable Logic Device Family March 2002, ver. 2.0 Features… Data Sheet • ■ Table 1. Mercury Device Features Feature Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 EP1M350 120,000 350,000 8 18 4,800

binary tree multipliers

Abstract: EP1M120 A7B9 A5B13
Contextual Info: Mercury Programmable Logic Device Family January 2003, ver. 2.2 Features… Data Sheet • ■ Table 1. Mercury Device Features Feature Typical gates HSDI channels LEs ESBs 1 Maximum RAM bits Maximum user I/O pins EP1M120 EP1M350 120,000 350,000 8 18

I.T.E power supply sc300

Contextual Info: AMDÌ1 P R E L IM IN A R Y Élan”SC300 Highly Integrated, Low-Power, 32-Bit Microcontroller DISTINCTIVE CHARACTERISTICS - Zero wait-state access with 70 ns, Page mode DRAMs • Highly integrated, single-chip CPU and system logic - Supports up to 16 Mbyte system memory

digital FIR Filter verilog code

Abstract: FIR filter matlaB design FIR filter matlaB simulink design verilog code for decimation filter verilog code for interpolation filter verilog code for linear interpolation filter digital FIR Filter VHDL code FIR Filter matlab VHDL code for polyphase decimation filter using D FIR Filter verilog code
Contextual Info: FIR Compiler MegaCore Function February 2001 User Guide Version 2.1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-FIRCOMPILER-2.1 FIR Compiler MegaCore Function User Guide Altera, ACEX, APEX, APEX 20K, FLEX, FLEX 10KE, MAX+PLUS II, MegaCore, MegaWizard, OpenCore, and Quartus are

thermodisc 37t series

Contextual Info: 37T Series Temperature Controls Moisture Resistant Temperature Control The 37T series of 3/4” 19mm bimetal disc temperature controls from Therm-O-Disc offers proven reliability in a moisture resistant sealed design. The snap-action of the bimetal disc provides