37064 Search Results

R765

Abstract: 75-RG214
Contextual Info: GSD R EVISIO N S ER 33571 WJM 12/06/91 CN 34652 A JCA 05/11/93 CN 37064 A KH 07/25/96 .68 REF. ACROSS FLATS STAMP: 91836 M39012/02-0006 1 2 0 1 -9 -5 XX XX 1201- 9 -5 5 /8 -2 4 UNEF-2A TH'O DÄfräDE NOTES: 1. FOR USE WITH M17/6-RG11, /62-RG144, /65-RG165,

RG144

Contextual Info: REVISIONS OJ CO ER 33571 WJM 12/06/91 r-o CN JCA O o 34652 A 05/11/93 CN 37064 A NO I KH o o o 07/25/96 CD 1201- 9 - 5 sc a le JCA0908 4:1 APPROX SURFACE AREA 1. FOR USE WITH M17/6-RG11, /62-RG144, /65-RG165, /74-213, /75-RG214. /77-RG216, /86-00001 CABLE.

vp44

Abstract: CY37064 CY37064V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY 37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks

cy37128

Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Contextual Info: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

Ultra37064

Abstract: CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress
Contextual Info: J ^ m n rn n : if : Y PRELIMINARY H 37064 - UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tc o = 4.5 ns • 64 m a cro cells in fo u r logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

37064

Abstract: 212-BOX
Contextual Info: Features • Efficient means of shipping or storing ESD sensitive circuit boards and other items • Provides ESD shielding with lid closed; “Faraday Cage” effect restricts electrostatic charges to exterior • For physical protection, convoluted foam secures items, minimizing movement

CY37064

Contextual Info: UltraLogic 64-Macrocell ISR™ CPLD — ts = 3.5 ns Features — tCo = 4 -5 ns • Product-term clocking 64 macrocells in four logic blocks In-System Reprogrammable™ ISR™ • IEEE 1149.1 JTAG boundary scan • Programmable slew rate control on individual l/Os

CY37032V

Contextual Info: CY37032V PREUM INAm UltraLogic 32-Macrocell ISR™ CPLD — tPD = 8.5 ns Features — ts = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable™ ISR™ includes: — tco = 6.0 ns Product-term clocking IEEE 1149.1 JTAG boundary scan

Contextual Info: PREUM INAm Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37032V

Abstract: CY37032
Contextual Info: 56V Back PRELIMINARY CY37032V UltraLogicTM 32-Macrocell ISRTM CPLD — tPD = 8.5 ns Features — tS = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • • • •

lem lta 100p

Abstract: lem la 100-P CY37064
Contextual Info: 37064 PR EU M IN Am UltraLogic 64-Macrocell ISR™ CPLD — ts = 4.0 ns Features — t co = 4.0 ns • 64 m a cro c ells in fo u r log ic blocks P ro d uct-term clo ckin g • In-S ystem R e p ro g ra m m ab le ™ IS R ™ JT A G -co m p liant o n-b oard p ro gram m in g

CY37064

Abstract: CY37064P44-167AC CY37032 CY37064V CY37064-200 CY37064P44-125AC
Contextual Info: 6 PRELIMINARY 37064 UltraLogic 64-Macrocell ISR™ CPLD — tS = 3.5 ns Features • 64 macrocells in four logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

Contextual Info: 37064V PRELIMINARY UltraLogic 3.3V 64-Macrocell ISR™ CPLD Features — tPD = 8.5 ns — tS = 5.0 ns • 64 macrocells in four logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — tCO = 6.0 ns Product-term clocking

AL102 ATES

Abstract: 2N2222A mps KR206 AD149 TIS58 TIS88 SFT353 2N2431 2N4265 BFY29
Contextual Info: SECOND BOOK OF TRAISKTIR EQUIVALENTS AIR SPIRTITOTER IT I.I.OMMI BERNARD BABANI publishing LTD The Grampians Shepherds Bush Road London W67NF England. Although every care Is taken with the preparation of this book, the publishers will not be responsible

CY37064VP44-125AC

Abstract: TEA 1112 A
Contextual Info: . „ n « PRELIMINARY 37064V UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 64 macrocells in four logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

CY37032V

Abstract: CY37032
Contextual Info: 56V PRELIMINARY CY37032V UltraLogicTM 32-Macrocell ISRTM CPLD — tPD = 8.5 ns Features — tS = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • • • • •

CS3705

Abstract: RFM10n50 RFM10N45
Contextual Info: Standard Power M O S F E T s - RFM10N45, RFM10N50 File Number 1788 Power MOS Field-Effect Transistors N-Channel Enhancement-Mode Power Field-Effect Transistors 10 A, 450 V - 500 V 0.6 1 N-CHANNEL ENHANCEMENT MODE fD S lo n *

Contextual Info: . „ n « PRELIMINARY 37064 UltraLogic 64-Macrocell ISR™ CPLD — ts = 3.5 ns Features — tco = 4.5 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ ISR™ • • • • • • • — JTAG-compliant on-board programming

Contextual Info: Ceramic LFCN-180+ LFCN-180 Low Pass Filter DC 1 to 180 MHz 50Ω Maximum Ratings Features Operating Temperature -55°C to 100°C Storage Temperature -55°C to 100°C RF Power Input* 8W max. at 25°C * Passband rating, derate linearly to 3W at 100°C ambient.

Contextual Info: Features - Efficient means of shipping or storing ESD sensitive circuit boards and other items • Provides ESD shielding with lid closed; “Faraday Cage” effect restricts electrostatic charges to exterior • For physical protection, convoluted foam secures items, minimizing movement

tlp 453

Abstract: CY37032V
Contextual Info: 6V CY37032V PRELIMINARY UltraLogicTM 32-Macrocell ISRTM CPLD — tPD = 8.5 ns Features — tS = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • • • • • •

CY37128V-83

Abstract: 35VCCI
Contextual Info: CY37128V PRELIMINARY UltraLogic 3.3V 128-Macrocell ISR™ CPLD — tPD = 10.0 ns Features — tS = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • •

CY37128P84-125JI

Contextual Info: 256 PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: . „ n « PRELIMINARY Ultra37128 UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes