3525 IC DATA SHEET Search Results

3525 PWM

Abstract: 3525 dead time control ic 3525 pwm application dc to dc converter ic 3525 pwm application 3525 "application note" pwm 3525 N-0516 3525 ic data sheet AA31001 driver 3525
Contextual Info: PHI 4.?. - f e " 3'" ~r - ' '' ' integrated circuits . W ., . „ „ . . ,., RL 3525 A „ Data Sheet Switched Mode Power Supply Control Circuit RL 35 25 A is a m on olithic bipolar Inte­ grated con tro l circu it intended for all types of sw itched m ode pow er sup­

Contextual Info: V SYNERGY Clockworks SY10ELT23 SY100ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR S E M IC O N D U C T O R DESCRIPTION FEATURES 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL outputs 24mA TTL outputs Flow-through pinouts

Contextual Info: V SYNERGY Clockworks SY10ELT23 SY100ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR S E M IC O N D U C T O R DESCRIPTION FEATURES 3.0ns typical propagation delay T h e S Y 1 0 /1 0 0 E L T 2 3 a re d u a l d iffe re n tia l P E C L -to -T T L tra n s la to rs .

ic 3525 pwm application

Abstract: 2149 RAM 3525 PWM Sunplus Caller ID ic 3525 internal block diagram 2149 ic 3525 8 pin pwm application 3845 PWM power supply application note P10P SPDC1000A1
Contextual Info: SPDC1000A1 1MB LCD CONTROLLER GENERAL DESCRIPTION The SPDC1000A1 is a powerful 8-bit CMOS single chip computer, it contains large RAM space to memorize reusable user data and large ROM space to allow user to establish high end application programs which need

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

AND8020

Abstract: E141 E241 MC100E241 MC100E241FN MC100E241FNR2 marking code e141
Contextual Info: MC100E241 5VĄECL 8ĆBit Scannable Register The MC100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2 D2D marking code
Contextual Info: MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2
Contextual Info: MC100E256 5V ECL 3-Bit 4:1 Mux-Latch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

AN1404

Abstract: AN1405 AND8020 MC100E336 MC100E336FN MC100E336FNR2
Contextual Info: MC100E336 5VĄECL 3ĆBit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω.

AN1404

Abstract: AN1405 AND8020 MC100E336 MC100E336FN MC100E336FNR2
Contextual Info: MC100E336 5V ECL 3-Bit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0−BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 − Q2) are specified for 50 Ω.

AND8020

Abstract: E336 MC100E337 MC100E337FN MC100E337FNR2
Contextual Info: MC100E337 5VĄECL 3ĆBit Scannable Registered Bus Transceiver The MC100E337 is a 3-bit registered bus transceiver with scan. The bus outputs BUS0–BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal

ic lm 3525

Abstract: IC LM 3210 lm 4050 ic 4050 spice MC100E122 MC100E122FN MC100E122FNR2 MC10E122 MC10E122FN MC10E122FNR2
Contextual Info: MC10E122, MC100E122 5VĄECL 9ĆBit Buffer The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V

MC10E142FN

Abstract: MC10E142FNR2 E142 MC100E142 MC100E142FN MC100E142FNR2 MC10E142
Contextual Info: MC10E142, MC100E142 5VĄECL 9ĆBit Shift Register The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input

AND8020

Abstract: E336 MC100E337 MC100E337FN MC100E337FNR2
Contextual Info: MC100E337 5V ECL 3-Bit Scannable Registered Bus Transceiver The MC100E337 is a 3-bit registered bus transceiver with scan. The bus outputs BUS0−BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 − Q2) are specified for 50 Ω. The bus outputs feature a normal

MC100E101

Abstract: MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2
Contextual Info: MC10E101, MC100E101 5VĄECL Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V • http://onsemi.com

3525 "application note"

Abstract: SECDED ic 4050 AN1404 AND8020 E160 MC100E193 MC100E193FN MC100E193FNR2 socket 775 pinout
Contextual Info: MC100E193 5VĄECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

MC100E167

Abstract: 100E167 MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Contextual Info: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop

MC100E175

Abstract: E175 MC100E175FN MC100E175FNR2 MC10E175 MC10E175FN MC10E175FNR2 E175 transistor
Contextual Info: MC10E175, MC100E175 5VĄECL 9ĆBit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the

MC10E155

Abstract: MC10E155FN MC10E155FNR2 MC100E155 MC100E155FN MC100E155FNR2
Contextual Info: MC10E155, MC100E155 5VĄECL 6ĆBit 2:1 MuxĆLatch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

MC100E154

Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

Contextual Info: MC100E193 5V ECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

Contextual Info: MC100EL30 5V ECL Triple D Flip−Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the

MC100E171

Abstract: MC100E171FN MC100E171FNR2 MC10E171 MC10E171FN MC10E171FNR2 D1C marking
Contextual Info: MC10E171, MC100E171 5VĄECL 3ĆBit 4:1 Multiplexer The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E163

Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
Contextual Info: MC10E163, MC100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.