3525 IC DATA SHEET Search Results

Contextual Info: V SYNERGY Clockworks SY10ELT23 SY100ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR S E M IC O N D U C T O R DESCRIPTION FEATURES 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL outputs 24mA TTL outputs Flow-through pinouts

Contextual Info: V SYNERGY Clockworks SY10ELT23 SY100ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR S E M IC O N D U C T O R DESCRIPTION FEATURES 3.0ns typical propagation delay T h e S Y 1 0 /1 0 0 E L T 2 3 a re d u a l d iffe re n tia l P E C L -to -T T L tra n s la to rs .

ic 3525 pwm application

Abstract: 2149 RAM 3525 PWM Sunplus Caller ID ic 3525 internal block diagram 2149 ic 3525 8 pin pwm application 3845 PWM power supply application note P10P SPDC1000A1
Contextual Info: SPDC1000A1 1MB LCD CONTROLLER GENERAL DESCRIPTION The SPDC1000A1 is a powerful 8-bit CMOS single chip computer, it contains large RAM space to memorize reusable user data and large ROM space to allow user to establish high end application programs which need

E142 wafer format

Abstract: HEL32 MR 4710 IC 300w power amplifier circuit diagram HEL05 klt22 HEL12 HEL31 HEL16 HLT22 HLT28
Contextual Info: DL140/D Rev. 6, Jan-2001 High Performance ECL Data ECLinPS and ECLinPS Lite™ High Performance ECL Device Data ECLinPS, ECLinPS Lite, and Low Voltage ECLinPS DL140/D Rev. 6, Jan–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved”

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2 D2D marking code
Contextual Info: MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

AN1404

Abstract: AN1405 AND8020 MC100E336 MC100E336FN MC100E336FNR2
Contextual Info: MC100E336 5VĄECL 3ĆBit Registered Bus Transceiver The MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs BUS0–BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω.

AND8020

Abstract: E336 MC100E337 MC100E337FN MC100E337FNR2
Contextual Info: MC100E337 5VĄECL 3ĆBit Scannable Registered Bus Transceiver The MC100E337 is a 3-bit registered bus transceiver with scan. The bus outputs BUS0–BUS2 are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal

MC10E142FN

Abstract: MC10E142FNR2 E142 MC100E142 MC100E142FN MC100E142FNR2 MC10E142
Contextual Info: MC10E142, MC100E142 5VĄECL 9ĆBit Shift Register The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input

MC100E101

Abstract: MC100E101FN MC100E101FNR2 MC10E101 MC10E101FN MC10E101FNR2
Contextual Info: MC10E101, MC100E101 5VĄECL Quad 4ĆInput OR/NOR Gate The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V • http://onsemi.com

MC100E175

Abstract: E175 MC100E175FN MC100E175FNR2 MC10E175 MC10E175FN MC10E175FNR2 E175 transistor
Contextual Info: MC10E175, MC100E175 5VĄECL 9ĆBit Latch With Parity The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs ODDPAR is HIGH if an odd number of the inputs are HIGH . The E175 can also be used to generate byte parity by using D8 as the

MC10E155

Abstract: MC10E155FN MC10E155FNR2 MC100E155 MC100E155FN MC100E155FNR2
Contextual Info: MC10E155, MC100E155 5VĄECL 6ĆBit 2:1 MuxĆLatch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic

MC100E154

Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
Contextual Info: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on

Contextual Info: MC100EL30 5V ECL Triple D Flip−Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the

MC100E171

Abstract: MC100E171FN MC100E171FNR2 MC10E171 MC10E171FN MC10E171FNR2 D1C marking
Contextual Info: MC10E171, MC100E171 5VĄECL 3ĆBit 4:1 Multiplexer The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E157

Abstract: MC100E157FN MC100E157FNR2 MC10E157 MC10E157FN MC10E157FNR2
Contextual Info: MC10E157, MC100E157 5VĄECL Quad 2:1 Multiplexer The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select SEL inputs. The individual select control makes the devices well suited for random logic designs.

MC100E164

Abstract: MC100E164FN MC100E164FNR2 MC10E164 MC10E164FN MC10E164FNR2 MAX5971
Contextual Info: MC10E164, MC100E164 5VĄECL 16:1 Multiplexer The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs SEL0, 1, 2, 3 control which one of the sixteen data inputs (A0 – A15) is propagated to the output. Special attention to the design layout results in a typical skew

MC100E158

Abstract: MC100E158FN MC100E158FNR2 MC10E158 MC10E158FN MC10E158FNR2
Contextual Info: MC10E158, MC100E158 5VĄECL 5ĆBit 2:1 Multiplexer The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input SEL . The 100 Series contains temperature compensation. • • • • • •

MC100E404

Abstract: MC100E404FN MC100E404FNR2 MC10E404 MC10E404FN MC10E404FNR2 ECL IC NAND
Contextual Info: MC10E404, MC100E404 5VĄECL Quad Differential AND/NAND The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

MC100E166

Abstract: MC100E166FN MC100E166FNR2 MC10E166 MC10E166FN MC10E166FNR2 0180T
Contextual Info: MC10E166, MC100E166 5VĄECL 9ĆBit Magnitude Comparator The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation.

MC100E156

Abstract: MC100E156FN MC100E156FNR2 MC10E156 MC10E156FN MC10E156FNR2 0180T
Contextual Info: MC10E156, MC100E156 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic

MC100E160

Abstract: MC100E160FN MC100E160FNR2 MC10E160 MC10E160FN MC10E160FNR2
Contextual Info: MC10E160, MC100E160 5VĄECL 12ĆBit Parity Generator/Checker The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input EN forces the Q output LOW. The 100 Series contains temperature compensation.

MC100E167

Abstract: MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Contextual Info: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be