3512K Search Results

Contextual Info: Advance information •■ 3512K16P 3512K18P Il II 3.3V 512K- 16 ‘18 pipeline burst synchronous SRAM Features • • • • • • • • • Organization: 5 2 4 ,2 8 8 w ord s x 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3 . 5 / 3 . 8 / 4 / 5 ns

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

siti

Abstract: nas77 3512K
Contextual Info: Features • • • • • • • • • Organization: 5 2 4 ,2 8 8 w ords x 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access'. 3 . 5 / 3 . 8 / 4 / 5 ns Fast UE access time: 3 . 5 / 3 . 5 / 3 . 8 / 4 ns Fully synchronous register-to-register operation

512KX24

Abstract: 128KX24
Contextual Info: ma DSP SOLUTIONS aSCTRONIC DÉSKSN& W C X24ASYNCHRONOUS FAMILY 128K AND 512Kx24 SV/3.3V EDI's x24 Asynchronous SRAM family is de­ signed in support of Analog Devices ADSP- * 2106x DSPs. The family includes densities of 128Kx24 and 5!2Kx24. The family of devices

bcm 4330

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Contextual Info: NEED IT NOW? BUY REMAN! SEE PAGE lxx xx xvi SOLUTIONS, SOLUTIONS. Q A r e q u a l i t y, c o s t , a n d t i m e i m p o r t a n t to you? A ELECTRICAL SOUTH! Q Do you spend too much of your valuable time dealing with too m a n y d i ff e r e n t r e p a i r v e n d o r s ?

Contextual Info: Advance information •■ I l 3512K16Z 3512K18Z A 3.3V 5 1 2K x 1 6 /1 8 synchronous burst SRAM with ZBT1 Features • • • • • • • • • • • • • • • • • • • Organization: 524,288 words x 16 or 18 bits ZBT architecture for efficient bus operation

Contextual Info: A Advance information •■ I l 3512K16Z 3512K18Z 3.3V 512Kx 16/18 synchronous burst SRAM with ZBT' Features • ZZ sleep m ode for lower power • Organization: 5 2 4 ,2 8 8 words x 16 or 18 bits • ZBT architecture for efficient bus operation

L8150

Contextual Info: Features • • • • • • • • • • • ZZ sleep m ode for lower power • Byte write enables • Single R /W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion •3 .3 V ± 5 % core power supply • 2.5V or 3.3V I/O operation with separate Vppg