512K18 Search Results

Contextual Info: Advance information •■ I l AS7C3512K16Z 512K18Z A 3.3V 5 1 2K x 1 6 /1 8 synchronous burst SRAM with ZBT1 Features • • • • • • • • • • • • • • • • • • • Organization: 524,288 words x 16 or 18 bits ZBT architecture for efficient bus operation

A301D

Abstract: A211D 4bc 82
Contextual Info: $GYDQFHLQIRUPDWLRQ $6&.3 $6&.3 9.ðSLSHOLQHEXUVWV\QFKURQRXV65$0  HDWXUHV • Multiple packaging options - Economical 100-pin TQFP package - Chip-scale fBGA package for smallest footprint • Byte write enables • Clock enable for operation hold

Contextual Info: $GYDQFHLQIRUPDWLRQ $6&.= $6&.= 9.ðV\QFKURQRXVEXUVW65$0ZLWK=%7Š HDWXUHV • ZZ sleep mode for lower power • Byte write enables • Single R/W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion

L8150

Contextual Info: Features • • • • • • • • • • • ZZ sleep m ode for lower power • Byte write enables • Single R /W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion •3 .3 V ± 5 % core power supply • 2.5V or 3.3V I/O operation with separate Vppg